{"id":1211955,"url":"https://alion.io/job/rebellions-soc-clock-reset-and-peripheral-architecture-engineer","title":"SoC Clock, Reset and Peripheral Architecture Engineer","company":{"id":173,"name":"Rebellions","domain":"rebellions.ai","url":"https://alion.io/company/rebellions","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greeting","truth_index":{"grade":"C","score":63,"open_postings":37,"ghost_share":0.622,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":48,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seongnam, South Korea"],"countries":["KR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":73000,"max_usd":169000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1777},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-01-28T13:20:51Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-21T06:43:16Z","board_verified":true,"closed_at":null,"days_open":265,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":265},"description":"About the Job\nWe are seeking a System Architecture Engineer to join our Architecture team and lead the definition of clock, reset, peripheral, and GPIO architectures across complex SoC systems. This role focuses on system-level architecture, spanning multi-chiplet, multi-chip, and board-level considerations, and plays a critical role in enabling scalable, robust, and reusable silicon platforms.\nThe ideal candidate will work closely with SoC architects, IP design, physical design, package/board and software/firmware engineers to ensure that system architecture decisions are coherent, extensible, and production-quality.\nResponsibilities and Opportunities\nDefine clocking and reset architecture at the system and SoC level, considering multi-chiplet, multi-chip package, board-level integration, power domain, clock domain, and reset domains\nArchitecting peripheral and GPIO subsystems to support diverse system use cases and physical configurations\nEnsure architectural consistency across SoC, package, board boundaries\nCollaborate with power architects to align clock/reset architecture with power states and DVFS strategies\nProvide architectural guidance during design exploration with design engineers\nKey Qualifications\nMaster’s or higher degree in Electrical Engineering, Computer Science, or a related field\n5+ years of experience in SoC and system architecture\nComprehensive understanding of the full SoC design, clocking/reset design principles, power/clock/reset domain interactions, peripheral and GPIO subsystem design\n전형절차\n서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격\n전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.\n전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.\n참고사항\n본 공고는 모집 완료 시 조기 마감될 수 있습니다.\n지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.\n채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.\n보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.\n담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.\n채용 관련 문의사항은 아래 메일 주소로 문의바랍니다. \n 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