{"id":1211958,"url":"https://alion.io/job/rebellions-socsubsystem-design-engineer","title":"SoC/Subsystem Design Engineer","company":{"id":173,"name":"Rebellions","domain":"rebellions.ai","url":"https://alion.io/company/rebellions","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greeting","truth_index":{"grade":"C","score":66,"open_postings":28,"ghost_share":0.571,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-26T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seongnam, South Korea"],"countries":["KR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":85000,"max_usd":173000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":316},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-01-28T13:07:14Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-25T08:02:56Z","board_verified":true,"closed_at":null,"days_open":241,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":241},"description":"About the Job\nAs a Senior SoC/Subsystem Design Engineer, you will lead the architecture and integration of next-generation AI acceleration systems. This role demands a high-level integration of RTL design expertise and system-level optimization to ensure robust performance and power under dynamic workloads. You will drive cross-functional collaboration to deliver high-reliability silicon from initial architecture to final bring-up.\nResponsibilities and Opportunities\nAI Architecture & Integration: Lead the architectural definition of SoC or Subsystem, RTL design, and system integration for high-performance AI acceleration SoCs\nCross-Functional Collaboration: Partner closely with verification, software, and backend teams to ensure seamless IP integration and full-stack system functionality\nDSP & Logic Implementation: Collaborate with DSP engineers to bridge the gap between complex algorithms and hardware implementation\nSilicon Bring-up & Validation: Drive the silicon bring-up process, leading hardware/software debugging to ensure mission-critical reliability\nInnovative System Design: Opportunity to apply advanced clock and power control design and methodologies to enhance SoC robustness and immunity against environmental perturbations\nKey Qualifications\n10+ years of experience in high-complexity RTL design using SystemVerilog or Verilog\nSubsystem Leadership: Proven track record of leading SoC subsystem designs from conceptual architecture to physical implementation\nAdvanced Toolchain Proficiency: * Simulation: Expert in VCS or Xcelium for debugging complex RTL issues and Gate Level Simulation issue\nQuality & Integration: Mastery of Lint, CDC, RDC, DFT, and Synthesis flows, along with automated integration tools like IP-XACT\nEnd-to-End Design Experience: Comprehensive understanding of the full SoC lifecycle, including power-on reset sequences and clock domain crossing\nIdeal Qualifications\nInfrastructure Design: Deep experience in designing and optimizing Clock, Reset, and Power Control Units\nMemory Management: Understanding of ARM MMU architectures and memory coherency protocols\n전형절차\n서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격\n전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.\n전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.\n참고사항\n본 공고는 모집 완료 시 조기 마감될 수 있습니다.\n지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.\n채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.\n보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.\n담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.\n채용 관련 문의사항은 아래 메일 주소로 문의바랍니다. \n ","description_format":"text","description_chars":2610,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-25T04:44:08Z"}],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.3,"p_room":0.28,"age_days":240,"expected_fill_days":53,"reasons":["conf:21","stale_co","velocity","ghost","win:tail","crowd:"],"computed_at":"2026-09-26T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/rebellions-socsubsystem-design-engineer","json_url":"https://alion.io/job/rebellions-socsubsystem-design-engineer.json","meta":{"generated_at":"2026-09-27T00:47:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":716,"day_limit":5000,"remaining_today":4284,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}