{"id":3986332,"url":"https://alion.io/job/regami-solutions-lead-rtl-design-engineer","title":"Lead RTL Design Engineer","company":{"id":4526816,"name":"Regami Solutions","domain":"regami.solutions","url":"https://alion.io/company/regami-solutions","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Chennai, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verification & Validation","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-09T21:35:00Z","employer_posted_date":null,"last_verified_at":"2026-11-09T21:35:00Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"Regami Solutions is looking for a Lead RTL Engineer with deep expertise in RTL design and SoC development. This role focuses on the architecture, design, and delivery of high-quality RTL for complex IP, subsystem, and SoC-level designs, with strong emphasis on microprocessor architectures, interconnects, memory subsystems, and high-speed interfaces.\n\nThe successful candidate will provide strong technical leadership, mentor engineers, and drive the delivery of robust, high-performance, and production-ready silicon designs that meet industry-leading quality, power, performance, and area (PPA) requirements.\n\nRequirements:\n\nAreas of Responsibility:\nContribute to RTL design and delivery across multiple IP, subsystem, and SoC-level projects.\nWork closely with system architects to define high-level specifications that are robust, scalable, and implementation-ready.\nInterface with verification and validation teams to ensure functional correctness, quality, and design robustness.\nCollaborate effectively with cross-functional R&D teams including Verification, Digital IP, Design Enablement, Emulation, Validation, and Software to achieve project milestones.\nDrive continuous improvement in design methodologies and best practices to achieve Zero-Defect silicon outcomes.\nEngage with Subject Matter Experts (SMEs) and technical leaders across architecture, systems, emulation, SoC design, software, physical design, and IP teams to influence technical direction and build strong engineering networks.\n\nQualifications:\nBachelor's or Master's degree in Electrical Engineering, Computer Science, or a related discipline.\n7+ years of hands-on experience in IP / Subsystem RTL Design; minimum 5+ years of relevant domain experience.\nStrong experience in testbench design and development using UVM methodology for IP, subsystem, and SoC verification.\nSolid understanding of microcontroller and microprocessor architectures, interconnects, and cache coherency mechanisms.\nExperience with industry-standard protocols such as AHB, AXI, CHI, and memory technologies including ROM, RAM, Flash, LPDDR, DDR3/DDR4, and memory controllers.\nProficiency in Verilog, SystemVerilog, C/C++, and Shell scripting.\nWorking knowledge of scripting languages such as Perl, TCL, or Python is an added advantage.\nStrong grasp of metric-driven verification, including functional and code coverage.\nExpertise in directed and constrained-random verification methodologies.\nGood understanding of formal verification techniques and assertion-based verification.\nExperience debugging designs pre- and post-silicon, both in simulation environments and on hardware benches.\nHands-on experience with SystemVerilog front-end tools including simulators, waveform viewers, lint, CDC, RDC, and related FE methodologies.\nStrong domain knowledge in clocking architectures, power management, system modes, debug, and security architectures.\nExcellent written and verbal communication skills.\n\nAdditional Plus Skills:\nExperience with high-speed peripherals such as DDR, PCIe, Ethernet.\nExposure to GPU, VPU (Video Processing Units), NICs, FlexNOC interconnects.\nExperience with Flash memory subsystems.\nSkills\nIP, RTL, SOC, Subsystem, SystemVerilog, UVM, Verilog","description_format":"text","description_chars":3222,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-11-09T21:35:00Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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