{"id":2143083,"url":"https://alion.io/job/renesas-electronics-associate-hardware-engineer","title":"Associate Hardware Engineer","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":76,"open_postings":101,"ghost_share":0,"stale_share":0.97,"repost_share":0,"time_to_fill_p50_days":33,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":11000,"max_usd":27000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":633},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":true},{"name":"Cadence Virtuoso","optional":true},{"name":"Linux","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Unix","optional":true}],"status":"closed","first_seen_at":"2026-10-07T07:05:07Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-19T06:37:30Z","board_verified":false,"closed_at":"2026-10-19T06:37:30Z","days_open":11,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":11},"description":"FIPV (Foundation IP Development VN) is responsible for the design, development, verification, and release of Foundation IP hard macros, IO libraries, and power-related IPs used in advanced semiconductor products.\nThis role covers activities from specification understanding through circuit design, physical layout, characterization cell/IP to generate timing, power and electrical behavior models, and chip-top integration support. The engineer will contribute to delivering high-quality IP solutions that enable successful product development across advanced technology nodes.\n Develop and optimize custom layout implementations for IO (GPIO, Peripheral IO), Power, and Hard Macro IPs on advanced semiconductor technologies (e.g. TSMC, GlobalFoundries...), working closely with technical experts from both Japan and Vietnam teams.\nPerform full-custom layout design for IO circuits, analog circuits, and low-power control circuits from schematic implementation through final layout release, ensuring compliance with IP specifications and quality requirements.\nConduct floorplan, device placement, routing, and layout optimization of hierarchical IP blocks while adhering to technology design rules, quality assurance standards, and manufacturability requirements.\nEnsure designs achieve targets for performance, power, area, reliability, ESD robustness, and silicon manufacturability.\nExecute physical verification activities including DRC, LVS, ERC, Antenna, and related validation checks, and perform root-cause analysis and debugging of verification issues.\nGenerate and maintain IP deliverables and library collateral, including GDSII, CDL, LEF, Liberty, NDM, and associated documentation required for downstream implementation flows.\nCollaborate with Chip Top, Product, and Physical Design teams to support integration, verification, and PPA (Performance, Power, Area) optimization at the chip level.\nAnalyze and address reliability concerns, including ESD, Electromigration (EM), IR Drop, and Latch-up, throughout the IP development cycle.\nDrive productivity and quality improvements through methodology enhancement, automation development, and continuous process optimization.\n Bachelor’s degree in Electronics Engineering, Electrical Engineering, Microelectronics, Computer Engineering, or related fields.\nStrong Academic background in semiconductor devices, ability to understand and analyze the physical behavior of CMOS circuits, parasitic effects, signal propagation, power distribution, and ESD protection mechanisms is highly desirable.\nStrong foundation in engineering physics and mathematics. Familiar with fundamental concepts such as Ohm's Law, Kirchhoff's Current and Voltage Laws (KCL/KVL), current flow, voltage, resistance, capacitance, and basic semiconductor physics.\nDemonstrated interest in semiconductor IP development, including circuit design, physical implementation, characterization, library development, and chip integration.\nFamiliarity with EDA tools is a plus (Cadence Virtuoso, Synopsys, Siemens/Mentor, etc.).\nKnowledge of Linux/Unix operating systems and scripting languages (Shell, Python, Perl, Tcl) is an advantage.\nStrong analytical and problem-solving skills.\nWillingness to learn advanced semiconductor technologies and design methodologies.\nGood communication and teamwork skills in a multicultural environment.\nAbility to work independently as well as collaboratively within global engineering teams.\nGood English reading and communication skills.\n Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.","description_format":"text","description_chars":4817,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Automotive Components","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-09T03:52:58Z"},{"event":"close","at":"2026-10-19T06:37:30Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/renesas-electronics-associate-hardware-engineer","json_url":"https://alion.io/job/renesas-electronics-associate-hardware-engineer.json","meta":{"generated_at":"2026-10-19T22:32:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1471,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3481},"rest":"https://alion.io/mcp/rest/get_company?id=3481"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frenesas-electronics-associate-hardware-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frenesas-electronics-associate-hardware-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frenesas-electronics-associate-hardware-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/renesas-electronics-associate-hardware-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frenesas-electronics-associate-hardware-engineer"}]}