{"id":3168266,"url":"https://alion.io/job/renesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies","title":"Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":75,"open_postings":108,"ghost_share":0,"stale_share":0.991,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":275500,"max":344500,"currency":"USD","period":"year","gross":null,"usd_annual":344500},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":true}],"status":"closed","first_seen_at":"2026-10-23T15:23:41Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-27T15:50:17Z","board_verified":false,"closed_at":"2026-10-27T15:50:17Z","days_open":4,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":4},"description":"This position will serve as the leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture. Expertise in architecture, design, validation, HW/SW optimization, and co-design is required. Experience in platform design and translating customer-facing requirements into system-level requirements is highly desirable.\nThe role encompasses workload characterization, solution integration, performance and power tradeoffs, the development of advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines.\nThe ideal candidate is a recognized technical leader with deep expertise in workload and performance analysis, AI workloads, HW/SW co-design, and SoC architecture. You will partner with product groups, platform teams, and executive leadership to define and analyze products and SoCs for performance and workload analysis, and help co-optimize using next-generation design methodologies that accelerate innovation and enable reuse across the organization.\nKey Responsibilities\nTechnical Leadership\nDefine and drive the strategic roadmap for workload analysis and performance for both IPs and products across the company.\n\nLead architecture performance reviews and technical direction for complex IP/SoC and subsystem developments.\n\nEstablish best practices for hardware/software co-design and model-based development.\n\nProvide technical leadership for cross-functional teams spanning architecture, design, verification, emulation, and software.\n\nAI-Driven Engineering Innovation\nDefine and analyze AI workloads and the performance required for these workloads.\n\nOrganizational Leadership\nBuild and lead high-performing engineering teams.\n\nMentor directors, principal engineers, and distinguished engineers.\n\nFoster collaboration across Central Engineering, Product Groups, and external partners.\n\nInfluence long-term semiconductor technology and platform strategy.\n\n Education\nMS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (Ph.D. highly desired).\n\nExperience\n15+ years of experience in semiconductor or SoC development.\n\n8+ years of technical leadership experience.\n\nProven experience leading performance and workload analysis and HW/SW co-optimization.\n\nTechnical Skills\nStrong understanding of:\nPerformance analysis\n\nWorkload analysis\n\nAI workloads\n\nSoC architecture and integration\n\nDigital design methodologies\n\nIP and subsystem development\n\nHardware/software co-design\n\nSoC verification methodologies\n\nHands-on experience with:\nPerformance and workload benchmarking\n\nVirtual platforms and executable specifications\n\nSoC performance modeling\n\nDesign and verification automation flows\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.","description_format":"text","description_chars":4478,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Processors, MCUs & AI Chips","Automotive Components","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-23T17:57:52Z"},{"event":"close","at":"2026-10-27T15:50:17Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 60 · green card filings: 30","filings_12m":60,"filings_prev_12m":78,"green_card_filings_12m":30,"median_offered_wage_usd":144222,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1}],"liveness":null,"pay":{"stated_usd_annual":344500,"is_top_pay":true},"html_url":"https://alion.io/job/renesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies","json_url":"https://alion.io/job/renesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies.json","meta":{"generated_at":"2026-10-28T18:22:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":25109,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3481},"rest":"https://alion.io/mcp/rest/get_company?id=3481"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frenesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frenesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frenesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/renesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frenesas-electronics-distinguished-engineer-de-or-senior-director-central-engineering-soc-design-modeling-methodologies"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3168266}},{"tool":"search_jobs","arguments":{"company":"renesas.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3168266},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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