{"id":2143288,"url":"https://alion.io/job/renesas-electronics-principal-fpga-emulation-engineer","title":"Principal FPGA Emulation Engineer","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":75,"open_postings":100,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":31,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":144000,"max_usd":274000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Agile","optional":true},{"name":"C++","optional":true},{"name":"Cadence Protium","optional":true},{"name":"MATLAB","optional":true},{"name":"Siemens Veloce","optional":true},{"name":"Simulink","optional":true},{"name":"Synopsys HAPS","optional":true}],"status":"closed","first_seen_at":"2026-09-25T23:32:11Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-21T03:10:35Z","board_verified":false,"closed_at":"2026-10-21T03:10:35Z","days_open":25,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":25},"description":"About the Role\nRenesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power-control architectures pre-silicon - proving out control loops, catching RTL issues early, and de-risking tape-out.\nThese FPGA platforms are emulation vehicles, not production hardware. Success is measured by how faithfully and how fast they reproduce the target silicon: functional equivalence to the golden ASIC RTL, real-time (or near-real-time) performance for closed-loop power and DSP validation, and deep visibility for pre-silicon debug.\nWhat You'll Do\nPartner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA - advising on FPGA-ability and turning architectural intent into a working, real-time emulation platform.\nAdapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design - handling clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state/bus conversion, and stubbing or modeling of analog/mixed-signal blocks.\nMap designs onto the FPGA fabric to fit and to hit emulation speed - steering resource inference (DSP/multiplier slices, block vs. distributed memory), clocking, and pipelining so the design achieves the real-time performance the validation requires.\nBuild the real-time environment around the digital core: model or interface to the analog and power stages (ADC/DAC/PWM, gate drivers, plant/converter models), including hardware-in-the-loop with real or emulated power hardware where needed.\nDevelop deep pre-silicon debug and visibility - logic analysis, long-run waveform capture, triggering, and assertions - and enable firmware/software co-development ahead of silicon.\nDefine and continuously improve the emulation methodology, RTL/FPGA-ability guidelines, flows, and automation (TCL/Python).\nProvide technical leadership: mentor engineers, lead reviews, and drive emulation and tooling decisions across the silicon and systems teams.\n Required Qualifications\nExtensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs.\nExpert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL.\nDeep understanding of FPGA internal architecture and primitives - DSP/multiplier slices, block and distributed RAM, carry chains, and clocking - and a proven ability to map designs onto these resources to fit large ASIC RTL and reach real-time emulation performance (memory/SRAM macro mapping, DSP inference, clock-enable conversion, control-set and fanout management).\nHands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.\nStrong command of the full FPGA implementation flow - synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) - on large Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus.\nHardware bring-up and debug experience: in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug.\nProficiency scripting for automation (TCL, Python).\nDemonstrated technical leadership - mentoring, reviews, and driving cross-team technical decisions.\nBS or MS in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).\nPreferred Qualifications\nReal-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages (ADC/DAC/PWM interfaces, plant/converter models).\nUnderstanding of digital power-conversion control and mixed-signal systems - converter topologies, control loops, PWM/PFM, and magnetics - to build faithful models and validate power-control architectures.\nFPGA DSP implementation and real-time emulation of DSP datapaths: FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC, including high-throughput techniques such as folding/unfolding.\nExperience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.\nModel-based design with Simulink and/or Xilinx System Generator.\nHigh-speed interface experience: JESD204B, PCIe, 1G/10G Ethernet, Aurora.\nASIC design or tape-out exposure, including DFT/scan considerations in emulation.\nAbility to architect and build a custom in-house FPGA prototyping platform - board architecture, high-speed PCB design, signal integrity, and bring-up - a plus as we may develop our own hardware in the future.\nEmbedded/microcontroller and firmware co-development experience (C/assembly); MATLAB, C/C++.\n Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.","description_format":"text","description_chars":6529,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Automotive Components","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-09T03:52:58Z"},{"event":"close","at":"2026-10-21T03:10:35Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 60 · green card filings: 30","filings_12m":60,"filings_prev_12m":78,"green_card_filings_12m":30,"median_offered_wage_usd":144222,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":23}],"liveness":null,"pay":null,"html_url":"https://alion.io/job/renesas-electronics-principal-fpga-emulation-engineer","json_url":"https://alion.io/job/renesas-electronics-principal-fpga-emulation-engineer.json","meta":{"generated_at":"2026-10-21T16:52:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":23781,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3481},"rest":"https://alion.io/mcp/rest/get_company?id=3481"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frenesas-electronics-principal-fpga-emulation-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frenesas-electronics-principal-fpga-emulation-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frenesas-electronics-principal-fpga-emulation-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/renesas-electronics-principal-fpga-emulation-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frenesas-electronics-principal-fpga-emulation-engineer"}]}