{"id":2158441,"url":"https://alion.io/job/renesas-electronics-senior-analog-engineering-manager-4","title":"Senior Analog Engineering Manager","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":75,"open_postings":100,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":31,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Leadership","role_family":"Leadership","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Johns Creek, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":140000,"max_usd":282000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1099},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":true}],"status":"live","first_seen_at":"2026-09-24T15:50:20Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-14T10:42:33Z","board_verified":true,"closed_at":null,"days_open":19,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":19},"description":"We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership.\nThe successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture\n Technical Leadership (DDR5 / DDR6)\nOwn and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.\nProvide technical oversight for critical analog and mixed-signal blocks, including:\nHigh-speed TX/RX datapaths\nAdvanced equalization, termination, and training circuits\nDLL/PLL-based clocking solutions for multi-GHz operation\nVoltage, reference generation, and power-aware IO design\nDrive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates.\nEnsure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction.\nLead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.\nPeople & Organization Leadership\nBuild, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces.\nSet technical direction, performance expectations, and development plans for senior and principal engineers.\nDrive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs.\nFoster a culture of technical rigor, ownership, and execution excellence.\nProgram & Cross-Functional Execution\nOwn DDR5/DDR6 PHY execution balancing schedule, quality, and risk\nPartner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, program management, and customers\nInterface with foundries, IP vendors, and standards bodies as needed to ensure successful delivery and future readiness.\nMethodology, Quality & Roadmap\nEstablish robust design and signoff methodologies for next-generation high-speed PHYs.\nDrive continuous improvement in simulation accuracy, mixed-signal verification, and silicon debug efficiency.\n Lead long-term DDR5 sustainment and DDR6 technology roadmap planning, including architectural trade-offs and scaling strategies.\nAnticipate challenges from data-rate scaling, power efficiency, and advanced process technologies\n Bachelor’s or Master’s degree in Electrical Engineering (PhD preferred).\n12+ years of experience in analog/mixed-signal IC design with deep focus on high-speed memory interfaces.\n5+ years of people-management and technical leadership experience.\nProven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5\nStrong expertise in: High-speed IO design and signal integrity, PLL/DLL and low-jitter clocking architectures,Mixed-signal verification and silicon validation, Advanced CMOS process considerations for IOs\nPreferred Qualifications\nDirect involvement in DDR6 architectural studies or early-stage development.\nExperience at advanced nodes (7nm, 5nm, and below).\nBackground in multi-generation memory PHYs or scalable PHY platforms.\nAbility to lead teams delivering multiple concurrent tape-outs.\nStrong written and verbal communication skills across technical and executive audiences.\nLeadership Profile\nHigh technical credibility with the ability to dive deep when needed\nStrong execution mindset with disciplined risk management\nEffective mentor and team builder\nStrategic thinker with a roadmap-driven approach to DDR evolution\nComfortable balancing hands-on engagement with organizational leadership\n Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.","description_format":"text","description_chars":5500,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Automotive Components","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-09T07:31:50Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 60 · green card filings: 30","filings_12m":60,"filings_prev_12m":78,"green_card_filings_12m":30,"median_offered_wage_usd":144222,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1}],"liveness":{"score":49,"band":"ok","label":"Likely open","p_open":1,"p_active":0.542,"p_room":0.9,"age_days":19,"expected_fill_days":31,"reasons":["conf:0","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":null,"html_url":"https://alion.io/job/renesas-electronics-senior-analog-engineering-manager-4","json_url":"https://alion.io/job/renesas-electronics-senior-analog-engineering-manager-4.json","meta":{"generated_at":"2026-10-14T13:02:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":16039,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3481},"rest":"https://alion.io/mcp/rest/get_company?id=3481"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frenesas-electronics-senior-analog-engineering-manager-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frenesas-electronics-senior-analog-engineering-manager-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frenesas-electronics-senior-analog-engineering-manager-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/renesas-electronics-senior-analog-engineering-manager-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frenesas-electronics-senior-analog-engineering-manager-4"}]}