{"id":3118677,"url":"https://alion.io/job/renesas-electronics-senior-digital-design-verification-engineer","title":"Senior Digital Design Verification Engineer","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":75,"open_postings":106,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":123000,"max_usd":226000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bash","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Agile","optional":true},{"name":"Cadence JasperGold","optional":true},{"name":"Cadence vManager","optional":true},{"name":"Cadence Xcelium","optional":true},{"name":"Formal Verification","optional":true},{"name":"Synopsys VCS","optional":true},{"name":"Synopsys Verdi","optional":true}],"status":"closed","first_seen_at":"2026-10-22T21:02:28Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-26T22:02:30Z","board_verified":false,"closed_at":"2026-10-26T22:02:30Z","days_open":4,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":4},"description":"Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications.\nYou will independently own verification of significant blocks and features from planning through closure. The role combines hands-on UVM development, coverage-driven verification, complex debug, and close collaboration with architecture, RTL design, firmware, analog, validation, and systems teams.\nResponsibilities\nOwn verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.\n\nDevelop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.\n\nBuild and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.\n\nDevelop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.\n\nDrive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.\n\nDebug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.\n\nAutomate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.\n\nCommunicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.\n\n Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n\n4 or more years of relevant digital design verification experience, or equivalent directly applicable experience.\n\nDemonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure.\n\nStrong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.\n\nExperience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria.\n\nHands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures.\n\nStrong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues.\n\nWorking knowledge of digital design fundamentals, including state machines, clocks and resets, interrupts, register interfaces, memories, and clock-domain crossings.\n\nProficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl.\n\nAbility to work independently and collaborate effectively across architecture, design, firmware, analog, validation, and systems teams.\n\nPreferred Qualifications\nExperience verifying complex SoCs, power management ICs, voltage regulators, digital controllers, or mixed-signal products.\n\nExperience verifying RTL interfaces to embedded processors, memory-mapped peripherals, and firmware-controlled hardware features.\n\nFamiliarity with PMBus, AVSBus, SVID or SVI3, I2C, SPI, or similar control and communication protocols.\n\nUnderstanding of telemetry, fault and alert handling, power sequencing, multiphase regulation, or digital control loops.\n\nExperience with Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi, or comparable tools.\n\nExperience with formal verification, gate-level simulation, silicon bring-up, or pre-silicon-to-silicon correlation.\n\nExperience improving regression infrastructure, coverage analytics, failure triage, or verification automation.\n\nWhat You Bring\nStrong technical ownership and a disciplined approach to verification completeness.\n\nAbility to reason beyond directed requirements and identify meaningful corner cases and feature interactions.\n\nClear communication of technical risk, progress, and signoff evidence.\n\nA collaborative mindset and interest in improving verification methodology and productivity.\n\n Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.","description_format":"text","description_chars":5934,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Automotive Components","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-22T23:26:32Z"},{"event":"close","at":"2026-10-26T22:02:30Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 60 · green card filings: 30","filings_12m":60,"filings_prev_12m":78,"green_card_filings_12m":30,"median_offered_wage_usd":144222,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":23}],"liveness":null,"pay":null,"html_url":"https://alion.io/job/renesas-electronics-senior-digital-design-verification-engineer","json_url":"https://alion.io/job/renesas-electronics-senior-digital-design-verification-engineer.json","meta":{"generated_at":"2026-10-27T00:34:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":640,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3481},"rest":"https://alion.io/mcp/rest/get_company?id=3481"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frenesas-electronics-senior-digital-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frenesas-electronics-senior-digital-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frenesas-electronics-senior-digital-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/renesas-electronics-senior-digital-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frenesas-electronics-senior-digital-design-verification-engineer"}]}