{"id":2158665,"url":"https://alion.io/job/renesas-electronics-senior-eda-physical-design-pnr-engineer","title":"Senior EDA Physical Design (PnR) Engineer","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":75,"open_postings":107,"ghost_share":0,"stale_share":0.991,"repost_share":0,"time_to_fill_p50_days":32,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":14500,"max_usd":33000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":8444},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Unix","optional":false},{"name":"Agile","optional":true},{"name":"Perl","optional":true}],"status":"live","first_seen_at":"2026-09-14T03:03:16Z","employer_posted_date":"2026-09-14","last_verified_at":"2026-11-14T04:59:32Z","board_verified":true,"closed_at":null,"days_open":61,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":61},"description":"Role Summary\nWe are seeking a highly motivated Senior EDA Physical Design Engineer with 3 to 8 years of industry experience to develop, deploy, and support advanced physical implementation methodologies for semiconductor designs.\nIn this role, you will combine hands-on physical design expertise with EDA methodology development and customer-facing technical support. You will evaluate emerging EDA technologies, develop robust and scalable RTL-to-GDSII implementation flows, and help engineering teams achieve their performance, power, area, runtime, and quality objectives.\nYou will work in a collaborative, global environment with product engineering, EDA teams and EDA vendors. The position is suited to an engineer who enjoys solving challenging implementation problems, developing production-quality design flows, and helping engineering teams adopt effective physical design methodologies.\nKey Responsibilities\nPhysical Design Implementation and Optimization\nPerform and support physical implementation activities, including floorplanning, power planning, placement, clock tree synthesis, routing, post-route optimization, and signoff preparation.\n\nAnalyze and resolve complex issues related to timing closure, congestion, routing, power integrity, design-rule compliance, and implementation quality.\n\nEvaluate quality-of-results trade-offs across timing, power, area, routability, runtime, and design robustness.\n\nSupport hierarchical and large-scale SoC implementation methodologies.\n\nCollaborate with relevant teams to achieve physical signoff readiness.\n\nMethodology Development and Deployment\nDevelop, validate, document, and deploy robust physical implementation methodologies and production-quality EDA flows.\n\nCreate reusable flow components, scripts, checks, reporting utilities, and automation infrastructure.\n\nStandardize implementation procedures and reports to improve consistency across projects.\n\nValidate methodology changes using representative designs, regression testing, and measurable quality-of-results criteria.\n\nSupport migration and adoption of new implementation platforms, including flow porting, validation, testing, and user onboarding.\n\nApply disciplined software engineering practices, including version control, modular design, testing, release management, and technical documentation.\n\nDrive improvements in flow robustness, scalability, usability, runtime, and quality of results.\n\nNew Technology Evaluation and Proof of Concept\nResearch and evaluate new EDA tool functions, implementation technologies, and semiconductor design methodologies.\n\nDefine technical evaluation criteria and conduct proof-of-concept activities using representative designs.\n\nCompare alternative tools and approaches based on quality of results, runtime, scalability, automation, usability, and integration requirements.\n\nIdentify technical limitations, deployment risks, and methodology improvement opportunities.\n\nDocument findings and present recommendations to engineering, product, and technical leadership teams.\n\nConvert successful evaluations into repeatable, supportable, and production-ready methodologies.\n\nExplore AI-assisted EDA capabilities and emerging automation technologies to improve engineering productivity and design outcomes.\n\nCross-Functional Collaboration\nWork closely with EDA R&D vendors, product engineering, and design teams to identify requirements and resolve implementation challenges.\n\nProvide structured technical feedback to product and R&D teams based on project deployment and customer experience.\n\nCollaborate across multiple sites and time zones to share best practices and maintain consistency across projects.\n\nParticipate in technical reviews, methodology planning, issue prioritization, and continuous-improvement initiatives.\n\nCommunicate technical risks, trade-offs, results, and recommendations clearly to technical and non-technical stakeholders.\n\nCustomer Engagement and Technical Support\nProvide hands-on technical support to semiconductor customers and internal project teams adopting physical implementation methodologies and EDA flows.\n\nInvestigate, reproduce, debug, and resolve complex issues related to tools, scripts, constraints, implementation methodologies, and design quality.\n\nGuide customers through flow setup, methodology adoption, optimization, and issue resolution.\n\nDeliver technical presentations, demonstrations, training materials, and implementation recommendations.\n\nCoordinate with product and R&D teams to escalate issues, communicate customer requirements, and track technical resolutions.\n\nBuild trusted technical relationships through responsiveness, ownership, sound engineering judgment, and clear communication.\n\nHelp ensure that deployed flows remain robust, scalable, and effective across multiple concurrent projects.\n\n Education and Experience\nBachelor's or Master's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, Microelectronics, Semiconductor Engineering, or a related technical discipline.\n\n3 to 8 years of relevant industry experience in ASIC physical design, semiconductor implementation, EDA or CAD engineering, physical implementation methodology development, or EDA applications engineering.\n\nTechnical Expertise\nStrong hands-on experience with synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure, congestion mitigation, and power and area optimization.\n\nPractical knowledge of RTL-to-GDSII implementation and physical signoff methodologies.\n\nExperience with Synopsys Fusion Compiler, IC Compiler II, Cadence Innovus or equivalent physical design tools.\n\nStrong understanding of static timing analysis, SDC constraints, clocking strategies, and setup and hold timing closure.\n\nExperience optimizing performance, power, area, congestion, runtime, and overall quality of results.\n\nFamiliarity with hierarchical SoC implementation, low-power design concepts, physical verification, and EDA flow integration.\n\nDebugging, Automation, and Problem Solving\nStrong analytical and problem-solving skills, with the ability to diagnose complex tool, flow, constraint, and design issues.\n\nProficiency in scripting and automation using Tcl, Python, or shell scripting in a Linux or Unix environment.\n\nAbility to develop maintainable, reusable, and well-documented flow infrastructure.\n\nExperience interpreting implementation reports, log files, timing reports, congestion data, and quality-of-results metrics.\n\nAbility to work independently, prioritize technical issues, and take ownership of deliverables through resolution.\n\nDemonstrated ability to learn and apply new tools, technologies, and methodologies.\n\nCommunication and Collaboration\nStrong written and verbal communication skills in English.\n\nAbility to explain complex implementation issues, technical trade-offs, and recommendations clearly.\n\nExperience working directly with customers, design teams, or EDA tool users.\n\nStrong presentation skills and the ability to deliver technical demonstrations, training, and methodology guidance.\n\nAbility to work effectively in a global, multi-site, and cross-functional engineering environment.\n\nCollaborative working style, customer-support mindset, and commitment to high-quality technical delivery.\n\nPreferred Skills\nAdvanced Tcl, Python, Perl, or shell scripting experience for EDA flow automation.\n\nHands-on experience with RTL-to-GDSII implementation and physically-aware synthesis.\n\nExperience developing or optimizing integrated Synopsys Fusion Compiler flows covering synthesis, placement, clock tree synthesis, routing, and timing closure.\n\nKnowledge of multi-mode, multi-corner analysis, advanced-node implementation challenges, and hierarchical SoC design.\n\nExperience deploying or standardizing physical implementation methodologies across multiple projects.\n\nFamiliarity with AI-assisted EDA workflows, data-driven optimization, or emerging semiconductor design technologies.\n\nExperience leading proof-of-concept activities or supporting globally distributed engineering teams.\n\n Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. 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