{"id":4270346,"url":"https://alion.io/job/renesas-electronics-senior-staff-electrical-engineer","title":"Senior Staff Electrical Engineer","company":{"id":3481,"name":"Renesas Electronics","domain":"renesas.com","url":"https://alion.io/company/renesas-electronics","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"B","score":75,"open_postings":107,"ghost_share":0,"stale_share":0.991,"repost_share":0,"time_to_fill_p50_days":32,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":false},{"name":"Cadence JasperGold","optional":false},{"name":"Cadence vManager","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Embedded C","optional":false},{"name":"Formal Verification","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C","optional":true}],"status":"live","first_seen_at":"2026-11-13T15:38:36Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-13T17:37:37Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Renesas is seeking a Senior Staff Digital Design Verification Engineer to lead verification\narchitecture, methodology and signoff for our Austin team's digitally controlled power-management\nICs, which power datacenter, AI accelerator, enterprise computing and networking systems. These\nchips combine a multiphase digital control loop, telemetry, fault and alert management, PMBus,\nAVSBus and high-speed power-management bus interfaces, an embedded microcontroller running\nproduction firmware, and non-volatile configuration, all integrated with high-performance analog.\nThis is a hands-on technical leadership role. You will own the verification strategy and tapeout\nsignoff for a controller program, architect the UVM-based environment in which our next generation\nof controllers will be verified, lead the migration of a large, mature directed-random SystemVerilog\nenvironment and its regression suite onto that platform, and raise the technical level of the\nverification team through review and mentorship. You set direction and are accountable for the\nresult, while still writing testbench code, debugging the hardest failures and making the call on what\nis and is not ready to ship\nResponsibilities:\nOwn the chip-level verification strategy, plan and signoff for a power-management controller program, from product requirements through tapeout, and present closure evidence and residual risk to engineering and program leadership.\nArchitect the next-generation UVM verification environment for the controller family: the analog interface and real-number modeling strategy, register model integration with firmware-driven and non-volatile configuration, protocol agents for the power-management buses, reuse across derivatives, and a migration path that keeps the existing regression suite running throughout.\nDefine and enforce verification methodology across the team: verification plan structure, coverage model and closure criteria, assertion and checker standards, coding guidelines and review practice.\nLead technical reviews of verification plans, testbench architecture, checkers and coverage models written by other engineers, and mentor senior and junior engineers toward full ownership of their blocks.\nDecide where formal verification, gate-level simulation, FPGA or emulation add value beyond simulation, and drive their adoption.\nOwn the verification infrastructure roadmap: regression dispatch on a compute grid, coverage merge and analytics, failure triage automation, and register and configuration generators, in Python, Perl and Tcl.\nLead debug of the most difficult failures across RTL, testbench, firmware, analog models and specification, and turn root causes into methodology and checker improvements.\nSupport silicon bring-up and validation, drive pre-silicon to silicon correlation, and run escape analysis that feeds back into the verification plan and methodology.\nEvaluate tools, verification IP and methodologies, and make build-versus-buy recommendations with cost and schedule justification.\nEstimate verification effort and staffing for new programs, and communicate status, risk and signoff evidence clearly to design, firmware, analog, validation, systems and program management.\n Required:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related field.\n8 or more years of digital or mixed-signal design verification experience with a Bachelor's degree, or 6 or more years with a Master's degree, or equivalent directly applicable experience.\nVerification lead for at least one full-chip tapeout, owning the verification plan, coverage closure and signoff recommendation, preferably on a mixed-signal product.\nArchitected and built a UVM environment from the ground up, including agents, score boards, register model, sequence library and coverage model, and sustained it across multiple projects or derivatives.\nExpert SystemVerilog and UVM: constrained-random stimulus, functional coverage modeling,\nSystemVerilog Assertions, and sound judgment about when directed, constrained-random or formal approaches fit the problem.\nMixed-signal verification depth: defining real-number or behavioral model requirements for analog blocks, running and debugging analog/digital co-simulation, and signing off models against transistor-level or silicon behavior.\n Hardware/firmware co-verification experience on an embedded processor: able to read and write embedded C, reason about register maps and non-volatile configuration, and decide whether a failure belongs to firmware, RTL, the model or the specification.\nDemonstrated technical leadership: reviewing other engineers' verification plans and code, mentoring, and setting methodology that a team actually follows.\nProficiency in Linux, Python and at least one of Perl or Tcl, with experience owning regression and coverage infrastructure on a grid scheduler such as LSF.\nClear written and spoken communication of technical risk and signoff evidence to engineers and to program leadership.\nPreferred:\nVerification of power-management ICs, voltage regulators, multiphase controllers or other digital control loops, including PWM generation, telemetry, fault and alert handling and power sequencing.\nLed a migration from a directed or module-based testbench to UVM on a live program without disrupting ongoing regressions.\nUVM register model integration with firmware-driven and non-volatile configuration, including generated register files.\nExpertise with PMBus, AVSBus, high-speed power-management bus protocols, I2C or SPI, and experience specifying or evaluating verification IP for them.\nFormal verification beyond connectivity checking: property checking, X-propagation, clock-domain crossing or reset verification with JasperGold or equivalent.\nCadence Xcelium, SimVision, Verdi, vManager and JasperGold, and mixed-mode simulation with Spectre AMS or equivalent.\nGate-level simulation, FPGA or emulation-based verification, silicon bring-up, and pre-silicon to silicon correlation and escape analysis.\nExperience estimating, staffing and scheduling verification for a chip program.\nWhat You Bring\nTechnical judgment: knowing which verification approach fits a problem, and knowing when\nsomething is actually done.\nOwnership of outcomes at the program level, not only of your own blocks.\nThe ability to set direction and build agreement across design, firmware, analog, systems and\nprogram management without relying on formal authority.\nA commitment to developing other engineers and leaving the team stronger than you found it.\nA practical approach to methodology change: improving how the team verifies without putting\ncurrent programs at risk.\n Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.","description_format":"text","description_chars":8376,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Automotive Components","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-11-13T17:37:37Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 60 · green card filings: 30","filings_12m":60,"filings_prev_12m":78,"green_card_filings_12m":30,"median_offered_wage_usd":144222,"route":null,"cap_exempt":false,"checked_at":"2026-11-12T07:36:15+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":23}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":32,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-11-13T19:28:45Z"},"pay":null,"html_url":"https://alion.io/job/renesas-electronics-senior-staff-electrical-engineer","json_url":"https://alion.io/job/renesas-electronics-senior-staff-electrical-engineer.json","meta":{"generated_at":"2026-11-13T19:28:45Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":38873,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3481},"rest":"https://alion.io/mcp/rest/get_company?id=3481"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frenesas-electronics-senior-staff-electrical-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frenesas-electronics-senior-staff-electrical-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frenesas-electronics-senior-staff-electrical-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/renesas-electronics-senior-staff-electrical-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frenesas-electronics-senior-staff-electrical-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4270346}},{"tool":"search_jobs","arguments":{"company":"renesas.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4270346},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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