{"id":1433810,"url":"https://alion.io/job/river-ai-design-verification-emulation-hardware","title":"Design Verification Emulation, Hardware","company":{"id":25477,"name":"River AI","domain":"river.ai","url":"https://alion.io/company/river-ai","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"C","score":65,"open_postings":17,"ghost_share":0.588,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Data Science","role_family":"Data Science","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":420000,"currency":"USD","period":"year","gross":null,"usd_annual":420000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agentic Workflows","optional":false},{"name":"AI Agents","optional":false},{"name":"C++","optional":false},{"name":"Cadence Palladium","optional":false},{"name":"Cadence Protium","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"CI/CD","optional":true},{"name":"Pre-training","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-09-28T22:53:52Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-01T15:54:59Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":2},"description":"At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.\nWho we are\nWe are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.\nAbout the Role\nWe are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff. You will also develop the models and infrastructure needed to support this work.\nWhat You’ll Do\nVerification Strategy & Planning: Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification based on runtime, fidelity, and debug needs. Define emulation workload goals and run acceptance criteria with DV block ownersEmulation Models: Build and maintain models and test components for simulation acceleration and emulator-hosted verification flows, balancing fidelity, performance, and debug visibility.\nEmulation Infrastructure: Develop and improve platform bring-up, compile, mapping, runtime, regression, and debug flows.Testbench and Workload Development: Adapt or develop test environments, transactors, stimulus, and software-driven workloads that run effectively on emulation platforms.\n\nEmulation Closure and Signoff: Track workload execution and failures, review results with DV block owners, and help close emulation-specific gaps. Provide emulation signoff as an input to overall IP and SoC verification signoff.\nEmulation Debug and Collaboration: Triage emulation compile, runtime, and test failures; use traces, waveforms, and platform diagnostics to isolate design, model, testbench, or infrastructure issues; partner with RTL and DV block owners to resolve them.\nAgentic AI for Emulation: Build and apply agentic workflows across workload planning, model and test preparation, platform setup, run orchestration, failure triage, result analysis, and closure reporting, improving engineering throughput while keeping results traceable and reviewable by DV owners.\nAutomation and Scripting: Build and maintain scripts and tools using Python, Tcl, Bash, or similar languages to improve platform usability, regression throughput, and results visibility.Skills and Qualification\nMinimum Qualifications:\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 5+ years of industry experience.\nHands-on experience with platforms such as Cadence Palladium/Protium, Synopsys ZeBu/HAPS, or comparable systems, including bring-up, model integration, compilation, execution, and debug.\nExperience building or adapting models and test environments for simulation acceleration, emulator-hosted verification, or both.\nStrong understanding of verification planning, regression strategy, and verification closure, with the ability to translate DV goals into emulation workload and run criteria.\nExperience verifying complex IP or SoCs, with an understanding of how verification needs change from block-level to system-level testing.\nProficiency in SystemVerilog, C/C++, and scripting languages such as Python, Tcl, or Bash.\nAbility to assess which tests and workloads are effective on emulation platforms, including tradeoffs among runtime, fidelity, observability, and debug.\nA collaborative mindset and a bias for action when working across design, verification, software, and infrastructure teams.\nPreferred Qualifications: (We encourage you to apply even if you don’t meet all of these)\nExperience using emulation for long-running software workloads, firmware and driver validation, system-level scenarios, or pre-silicon software bring-up.\nBackground developing synthesizable test components, transactors, behavioral models, or emulation-friendly replacements for simulation models.\nExperience with UVM-based verification environments and adapting them for acceleration or emulation.\nFamiliarity with coverage-driven verification and SystemVerilog Assertions (SVA).\nExperience using emulation workloads for performance verification and power estimation.\nExperience with high-performance silicon such as CPUs, GPUs, AI accelerators, or complex SoCs.\nExperience with workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.\nLogistics & Benefits\nLocation: This role is based in Austin, Texas or Palo Alto, California.\nCompensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.\nVisa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.\n Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.","description_format":"text","description_chars":5513,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Unlimited PTO"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["Foundation Models","AI Chips & Accelerators","AI Development Tools"],"lifecycle":[{"event":"open","at":"2026-09-29T02:20:05Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":47,"reasons":["conf:2","stale_co","velocity","win:early"],"computed_at":"2026-10-01T05:45:00Z"},"pay":{"stated_usd_annual":420000,"is_top_pay":true},"html_url":"https://alion.io/job/river-ai-design-verification-emulation-hardware","json_url":"https://alion.io/job/river-ai-design-verification-emulation-hardware.json","meta":{"generated_at":"2026-10-01T19:09:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1610,"day_limit":5000,"remaining_today":3390,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}