{"id":3258421,"url":"https://alion.io/job/riverlane-phd-engineering-internship-2027","title":"PhD Engineering Internship 2027","company":{"id":51525,"name":"Riverlane","domain":"riverlane.com","url":"https://alion.io/company/riverlane","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":75,"open_postings":12,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":39,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Boston, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":55,"max":null,"currency":"USD","period":"hour","gross":null,"usd_annual":110000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-20T14:28:18Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-28T10:16:52Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"PhD Internship 2027: Engineering - Boston\n Boston, US | Full-time | Fixed-term| Hybrid\nSalary: $55.70 per hour, DOE\nAbout us\nRiverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in materials and climate science to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent, and passion.\nHaving raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast. \nAbout the role\nDelivering practical quantum error correction requires tightly integrated quantum and classical systems. Decoding algorithms must process large volumes of error data within demanding latency, bandwidth, compute and power constraints.\nAs an engineering Intern, you will investigate the classical computing architectures needed to support scalable, fault-tolerant quantum computers. Your project will sit at the intersection of quantum error correction, computer architecture and hardware-software co-design.\nDepending on the project, you could explore efficient QEC decoding or predecoding methods, model the classical resources required by fault-tolerant quantum programs, or investigate how decoding workloads can be distributed across different levels of a computing system.\nYou will work alongside Riverlane’s researchers and engineers in Cambridge, Massachusetts, with support from a dedicated supervisor. Your work will contribute to our understanding of how QEC systems can meet the performance requirements of increasingly large quantum computers.\n\nWhat you will do\n\nContribute to a research project focused on the classical systems and architectures required for scalable quantum error correction\nInvestigate methods for reducing the compute, communication, memory, latency or power requirements associated with QEC\nDevelop algorithms, simulations or architectural models to evaluate potential approaches\nExplore trade-offs between decoding performance, logical error suppression and classical resource requirements\nConsider how QEC workloads could be implemented across software, FPGA, ASIC or other computing architectures\nCollaborate with researchers and engineers working across QEC theory, decoding, software and hardware\nAnalyse results and communicate your findings through technical discussions, presentations and written reports\nProduce clear, reproducible research code and supporting documentation\n\n What we need\n\nYou must be currently pursuing a PhD in Computer Science, Computer Engineering, Electrical Engineering, Physics, Mathematics or another related technical field\nResearch experience in at least one of the following areas:\nQuantum error correction or fault-tolerant quantum computing\nComputer architecture or quantum-classical systems\nDecoding algorithms or error-correcting codes\nFPGA, ASIC or digital hardware design\nExperience developing computational models, simulations or research software\nProficiency in Python, C, C++ or another relevant programming language\nA strong understanding of computer systems and architecture\nExcellent analytical and problem-solving skills\nThe ability to communicate complex technical ideas clearly\nThe ability to take initiative and work effectively with researchers and engineers from different disciplines\nAuthorisation to work in the United States for the duration of the internship\n\n Even better if…\n\nYou have experience researching quantum LDPC or surface codes\nYou are familiar with QEC decoding or predecoding techniques\nYou have explored the classical resource requirements of fault-tolerant quantum computing\nYou have experience with hardware-software or compiler-hardware co-design\nYou have worked with RTL, SystemVerilog, FPGA or ASIC development workflows\nYou understand the latency, bandwidth or power constraints affecting quantum control and decoding systems\nYou have experience with scientific computing, quantum circuit simulation or QEC simulation tools\nYou have contributed to academic publications, open-source software or collaborative research projects\n\nImportant notes\nYou must be legally authorized to work in the United States for the duration of the internship\nIf you intend to work under Curricular Practical Training (CPT), Optional Practical Training (OPT) or another form of student employment authorization, you are responsible for obtaining the necessary approval before your start date\nAny offer of employment will be contingent upon verification of your identity and authorization to work in the United States, as required by law\nYou must be available to work full-time for 10 to 12 weeks\nYou will be required to sign an agreement assigning ownership of intellectual property produced during your internship to Riverlane\nThis internship is based at our US office in Cambridge, Massachusetts\nHow to apply\nPlease upload your CV and a cover letter.\nYour CV should include details of your education, research experience and relevant technical skills. Your cover letter should explain why you are applying for the internship and the skills and experience you would bring to the role.\nDeadline\nPlease submit your application by November 6th, 2026\nPay and Expenses\n We will reimburse reasonable expenses incurred as part of your role, such as approved travel to meetings or conferences. We are unable to cover the cost of travelling to Cambridge, Massachusetts at the beginning or end of the internship or accommodation during the internship.\nWhat you can expect from us\nYou can expect a diverse and collaborative working environment that brings together experts in software and hardware development, quantum information theory, physics, mathematics and other technical fields. Our global team represents more than 20 nationalities.\nWe also provide free snacks and refreshments and organize regular social and cultural events.\nIf you have any questions, please contact .\nRiverlane is an equal opportunity employer. We welcome qualified applicants and consider them for employment without regard to race, color, religion, creed, sex, pregnancy, sexual orientation, gender identity or expression, national origin, ancestry, age, disability, genetic information, marital status, military or veteran status, or any other characteristic protected by applicable federal, state or local law.\nWe know that strong candidates may not meet every requirement listed. If you are interested in the opportunity and believe your experience could be relevant, we encourage you to apply.\nRiverlane provides reasonable accommodations to applicants with disabilities. If you require an accommodation during the application or interview process, please let us know. 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