{"id":3258451,"url":"https://alion.io/job/riverlane-verification-senior-verification-engineer","title":"Verification / Senior Verification Engineer","company":{"id":51525,"name":"Riverlane","domain":"riverlane.com","url":"https://alion.io/company/riverlane","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":75,"open_postings":12,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":39,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cambridge, United Kingdom"],"countries":["GB"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":60000,"max":88000,"currency":"GBP","period":"year","gross":null,"usd_annual":117695},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-02-04T11:28:24Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-27T06:46:23Z","board_verified":true,"closed_at":null,"days_open":264,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":264},"description":"Cambridge, UK | Full-time | Permanent | Hybrid \nSalary: £60,000 to £88,000 (DOE) + Bonus + Benefits \nThe salary range for this role is broad, as we are able to consider varying levels of experience. Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements.\nWe will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter. \nAbout us \nRiverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion. \nHaving raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast. \nAbout the role\nWe have an exceptional opportunity for a Verification / Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems. \nIn this exciting role you'll have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way. \nWhat you will do \nAs a Verification / Senior Verification Engineer at Riverlane, you will: \nProactively work with designers and architects to define verification plans based on design specifications. You will take full ownership of detailed test strategies across block-level and system-level designs. \nDevelop and implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests to ensure every part of the system performs flawlessly. \nMaintain the health and evolution of the design verification environment, tracking of regressions, coverage metrics and bugs to ensure our systems meet the highest standards of quality and reliability. \nWhat we need \nDemonstrable commercial experience in functional verification, including ownership of verification planning and strategy. \nProven experience of testbench design with verification frameworks like UVM/OVM. \nKnowledge of SystemVerilog assertion (SVA). \nExposure to different programming languages, such as C, C++ and Python. \nA proactive person who can independently define the scope of work. \nA collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback. \nAbility to work effectively with ambiguity and changing requirements. \nExperience debugging across RTL, simulation, and hardware \nEven better if… \nFormal verification experience. \nWhat can you expect from us \nA comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme \nEquity, so that our team can share in the long-term success of Riverlane \n28 days annual leave, plus bank holidays and enhanced family leave \nA diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities \nA learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets \n\nHow to apply \nPlease upload a CV and covering letter by clicking 'Apply Now'. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role. \nWe review CVs as we receive them and interview as soon as we have applications that look like a good match. We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. \nIf you have any queries, please contact . \nEveryone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. \nWomen and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you. \nIf you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help. \nGDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. 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