{"id":1399925,"url":"https://alion.io/job/roguebeam-sr-digital-rtl-engineer","title":"Sr. Digital RTL Engineer","company":{"id":3787219,"name":"Roguebeam","domain":"roguebeam.com","url":"https://alion.io/company/roguebeam","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seattle, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":130000,"max_usd":244000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":910},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-22T18:11:33Z","employer_posted_date":"2026-09-22","last_verified_at":"2026-09-30T21:00:34Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"About Roguebeam\nRoguebeam is a startup developing advanced phased array systems for communications and radar applications. We design and manufacture complete systems in-house-RF, antenna, PCB, ASIC/digital, and DSP-giving our engineers end-to-end ownership of the technology and a direct line of sight from algorithm to deployed system.\nWe’re early, we’re growing fast, and the people who join us now will shape both the technology and the company.\nThe Role\nWe're looking for a Senior Digital RTL Engineer to own digital control, beamforming, and interface logic at the heart of our phased-array solutions. As one of our early senior digital hires, you will not just execute against a spec-you will contribute to architecture and design methodology, take blocks from concept through silicon or FPGA bring-up, and help shape how the team works as it grows.\nYou'll own digital RTL design from architecture through synthesis, timing closure, and silicon/FPGA validation, working closely with RFIC, antenna, and DSP teams. The decisions you make will ripple through every product we build.\nResponsibilities\nDesign and implement production-quality digital RTL (SystemVerilog/Verilog) for beamformer control, phase/amplitude control interfaces, calibration logic, high-speed data paths, and system-level digital blocks\n\nDrive designs from specification and architecture definition through RTL coding, synthesis, timing analysis, place-and-route support, and silicon/FPGA validation\n\nPerform functional simulation, lint, CDC analysis, and timing closure; collaborate on verification planning and coverage for your blocks\n\nWork with RFIC, antenna, and DSP teams to define digital interfaces, control protocols, and system-level requirements\n\nSupport lab bring-up, debug, and design iteration of fabricated ASICs or FPGA-based prototypes\n\nImprove RTL coding standards, review designs from peers, and mentor more junior engineers as the team grows\n\nContribute to technical strategy, design reviews, documentation, and the digital design methodology\n\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related field\n\n7-10 years of relevant experience in digital RTL design for ASICs or FPGAs\n\nStrong proficiency in SystemVerilog/Verilog and industry-standard tools (e.g., Cadence/Synopsys synthesis and STA, simulation environments, lint/CDC tools)\n\nSolid command of digital design fundamentals: synchronous design, timing closure, clock-domain crossing, finite-state machines, and high-speed interfaces\n\nProven experience taking designs through synthesis, timing closure, and post-silicon or FPGA validation\n\nDemonstrated ability to own non-trivial blocks end-to-end and work across RFIC, DSP, and implementation teams\n\nPreferred Qualifications\nMSc or PhD with a focus on digital design, computer architecture, or VLSI\n\nExperience designing digital control logic for RF beamformers, phased arrays, or similar high-performance systems\n\nFamiliarity with high-speed serial interfaces, AXI/APB buses, and low-power design techniques\n\nBackground in communications (e.g., 5G/6G, satellite) or radar system requirements\n\nScripting (Python/Tcl) for design automation and flow development\n\nPrior work on phased-array or multi-antenna systems from concept through fielded product\n\nWhy Roguebeam\nThis is a rare ground-floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeeds-and a corresponding upside as we grow. Because we build the entire system in-house, you'll see your RTL designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. You'll have real ownership and a seat at the table on technical direction.\nThis position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.","description_format":"text","description_chars":3886,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-28T14:53:40Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":7,"expected_fill_days":42,"reasons":["conf:1","velocity","win:early"],"computed_at":"2026-09-30T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/roguebeam-sr-digital-rtl-engineer","json_url":"https://alion.io/job/roguebeam-sr-digital-rtl-engineer.json","meta":{"generated_at":"2026-10-01T03:33:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3058,"day_limit":5000,"remaining_today":1942,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}