{"id":1399930,"url":"https://alion.io/job/roguebeam-sr-dsp-rtl-engineer","title":"Sr DSP / RTL Engineer","company":{"id":3787219,"name":"Roguebeam","domain":"roguebeam.com","url":"https://alion.io/company/roguebeam","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seattle, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":129000,"max_usd":242000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":910},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Quantization","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-28T20:37:30Z","employer_posted_date":"2026-08-28","last_verified_at":"2026-10-02T19:43:23Z","board_verified":true,"closed_at":null,"days_open":35,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":35},"description":"About Roguebeam\nRoguebeam is a startup developing advanced phased array systems for communications and radar applications. We design and manufacture complete systems in-house-RF, antenna, PCB, ASIC/digital, and DSP-giving our engineers end-to-end ownership of the technology and a direct line of sight from algorithm to deployed system.\nWe’re early, we’re growing fast, and the people who join us now will shape both the technology and the company.\nThe Role\nWe’re looking for a Senior DSP / RTL Engineer who can own both the signal processing algorithms and their efficient digital implementation for our phased array solutions. As one of our early senior digital hires, you will define processing architecture, develop beamforming and adaptive algorithms, and implement key blocks in RTL-bridging the gap from concept to silicon/FPGA.\nYou’ll work end-to-end: algorithm design and modeling, fixed-point conversion, RTL coding and synthesis, timing closure, and lab validation. The decisions you make will directly shape system capability and product differentiation.\nResponsibilities\nDevelop and refine DSP algorithms for digital beamforming, adaptive nulling, channel estimation, calibration, and interference mitigation in communications and radar phased arrays\n\nOwn algorithm architecture from high-level floating-point models (MATLAB/Python) through fixed-point design, quantization analysis, and bit-true modeling\n\nDesign and implement digital RTL (SystemVerilog/Verilog) for DSP datapaths, control logic, beamforming engines, high-speed interfaces, and supporting blocks\n\nDrive RTL designs through synthesis, timing analysis, lint/CDC checks, place-and-route support, and silicon/FPGA validation\n\nDefine performance requirements and hardware architecture trade-offs (throughput, latency, area, power); optimize implementations for efficient resource utilization\n\nPerform system-level simulations and link analyses to quantify algorithm and implementation impact on overall array performance (SINR, EVM, detection range, etc.)\n\nSupport lab bring-up, debug, and iterative refinement of algorithms and RTL on FPGA/ASIC prototypes based on measured data\n\nContribute to technical strategy, design reviews, documentation, and mentoring as the team grows\n\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, or a related field\n\n7-10 years of relevant experience spanning digital signal processing algorithm development and digital RTL design for ASICs or FPGAs\n\nStrong proficiency with MATLAB and/or Python for algorithm design, simulation, and fixed-point analysis\n\nProven hands-on experience writing production-quality SystemVerilog/Verilog RTL, including synthesis, timing closure, lint, and CDC analysis\n\nSolid foundation in DSP fundamentals: multi-rate processing, adaptive filtering, array signal processing, estimation theory, and numerical considerations for fixed-point arithmetic\n\nDemonstrated ability to translate algorithms into efficient real-time hardware implementations\n\nPreferred Qualifications\nMSc or PhD with a focus on signal processing, communications, VLSI, or radar systems\n\nDirect experience with digital beamforming, adaptive arrays, MIMO processing, or space-time adaptive processing (STAP)\n\nBackground in communications (e.g., 5G/6G, satellite) or radar system requirements and performance metrics\n\nExperience taking designs from algorithm through RTL, synthesis, timing closure, and post-silicon or FPGA validation\n\nFamiliarity with high-speed interfaces, AXI/APB buses, low-power design techniques, and industry-standard EDA tools (Cadence/Synopsys)\n\nPrior work on phased-array or multi-antenna systems from concept through fielded product\n\nWhy Roguebeam\nThis is a rare ground-floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeeds-and a corresponding upside as we grow. Because we build the entire system in-house, you’ll see your algorithms and RTL designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. You’ll have real ownership and a seat at the table on technical direction.\nThis position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.","description_format":"text","description_chars":4303,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-28T14:53:40Z"}],"liveness":{"score":54,"band":"ok","label":"Likely open","p_open":1,"p_active":0.721,"p_room":0.75,"age_days":34,"expected_fill_days":41,"reasons":["conf:1","velocity","win:late"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/roguebeam-sr-dsp-rtl-engineer","json_url":"https://alion.io/job/roguebeam-sr-dsp-rtl-engineer.json","meta":{"generated_at":"2026-10-03T04:00:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4013,"day_limit":5000,"remaining_today":987,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}