{"id":3400319,"url":"https://alion.io/job/rosaiclabs-ai-accelerator-design-verification-engineer-full-time","title":"AI Accelerator Design Verification Engineer - Full Time","company":{"id":4483163,"name":"RosaicLabs","domain":"rosaiclabs.com","url":"https://alion.io/company/rosaiclabs","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":125000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"ONNX","optional":true},{"name":"Python","optional":true},{"name":"PyTorch","optional":true},{"name":"Rust","optional":true},{"name":"TensorFlow","optional":true},{"name":"TensorFlow C++","optional":true}],"status":"live","first_seen_at":"2026-10-05T23:58:51Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-31T06:13:15Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"Join our hardware team as AI Accelerator Design verification engineer verifying the state of the art AI chip, with hands-on ownership of verification environments from test plan through coverage closure and SI bring-up.\nWhat you'll do\nDevelop verification plans for AI accelerator blocks: tensor processing, fabric / network-on-chip, and SoC flows\nWrite and debug SystemVerilog/UVM testbenches, checkers, stimulus, scoreboards, and reference models for your assigned block or subsystem\nBuild emulation-friendly testbenches: synthesizable, transactor-based environments that run the same tests in simulation and on emulators or FPGA prototypes\nUse agentic AI tools across the verification workflow: generating test plans from specifications, writing and reviewing testbench code, triaging regression failures, root-causing bugs, and analyzing coverage. Review and validate everything the agents produce.\nVerify numerical correctness of compute datapaths (FP*) against bit-accurate golden models\nRun real ML kernels and random programs on the RTL, co-simulated against an ISA/architectural reference model\nDefine, implement, and close functional and code coverage goals, analyzing holes and driving them to closure\nDebug failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs\nApply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency\nRun and maintain regressions across simulation, emulation, and FPGA platforms, and track bug trends and verification progress metrics\nPartner with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals\nParticipate in microarchitecture, RTL, and verification reviews, and write technical documentation\nWhat we're looking for\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.\nStrong foundation in AI accelerator and computer architecture and digital design, with solid understanding of following:\nTensor cores and SIMT / SIMD / vector processing\nFloating-point / computer arithmetic, including reduced-precision formats\nOn-chip memories, scratchpads, and DMA engines\nCache hierarchy, memory systems, and HBM/DRAM interfaces\nNetwork-on-chip and on-chip interconnects\nDataflow, scheduling, and synchronization across many compute cores\nWorking knowledge of modern AI accelerator flows and ISAs, including familiarity with ISA simulators or reference models\nProficiency in System Verilog, C/C++, assembly\nFamiliarity with emulation-friendly verification (synthesizable testbenches, transactors) is a plus\nHands-on experience using agentic AI tools across the engineering workflow: delegating multi-step tasks to agents, writing clear instructions and context, and checking their results critically\nScripting experience for automation, test generation, regression management, or data analysis, such as Python, Tcl, or Rust\nExposure to ML frameworks or workloads (PyTorch, TensorFlow, or ONNX) is a plus","description_format":"text","description_chars":3148,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-28T14:14:05Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 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