{"id":3400318,"url":"https://alion.io/job/rosaiclabs-ai-accelerator-physical-design-engineer-full-time","title":"AI Accelerator Physical Design Engineer - Full Time","company":{"id":4483163,"name":"RosaicLabs","domain":"rosaiclabs.com","url":"https://alion.io/company/rosaiclabs","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Operations","role_family":"Operations","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Austin, United 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area (PPA) targets, including optimization of datapath-heavy and high-fanout structures\nManage power delivery and density: power grid design, IR-drop and electromigration analysis, and thermal-aware implementation\nImplement low-power techniques such as clock gating, power gating, multi-Vt, and multi-voltage domains\nRun static timing analysis, signal-integrity, and physical verification (DRC/LVS) signoff across corners and modes\nPartition and implement hierarchical designs, including budgeting and integration of replicated blocks\nWork with architecture, RTL, DFT, and verification teams to co-optimize design for physical implementability\nDevelop and maintain automation for flows, regressions, and QoR tracking\nSupport silicon bring-up and correlate post-silicon results with pre-silicon predictions\nWhat we're looking for\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field \n5+ years of industry experience in high performance, low power physical design\nHands-on experience taking complex digital designs through synthesis, place-and-route, and signoff at advanced process nodes\nStrong understanding of timing closure, clocking, and static timing analysis, including OCV and multi-corner multi-mode analysis\nExperience with power integrity: power grid design, IR drop, and electromigration\nExperience with physical verification (DRC/LVS) and fixing violations\nFamiliarity with accelerator or compute-array architectures, such as systolic arrays, SIMD/vector engines, and large on-chip memories\nProficiency with industry-standard EDA tools (see Tools & Technologies)\nScripting skills in Tcl, Python, or Perl for flow automation\nStrong debugging skills and the ability to work with RTL, architecture, and DFT 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