{"id":3400320,"url":"https://alion.io/job/rosaiclabs-cpu-design-verification-engineer-full-time","title":"CPU Design Verification Engineer - Full Time","company":{"id":4483163,"name":"RosaicLabs","domain":"rosaiclabs.com","url":"https://alion.io/company/rosaiclabs","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":125000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Rust","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-05T23:48:12Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-29T19:57:35Z","board_verified":true,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":23},"description":"What you'll do\nDrive CPU verification strategy, develop test plans for functional blocks based on specifications targeting micro-architectural & ISA features,\nArchitect, build and maintain SystemVerilog/C++ based testbench components, including stimulus generators, checkers, scoreboards, monitors, and reference models\nDevelop directed and pseudo-random tests from Random Instruction Generators to verify CPU functionality and stress corner cases\nDefine, implement, and close functional and code coverage goals, analyzing holes and driving them to closure\nDebug & root-cause failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs\nPartner cross-functionally with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals.\nApply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency\nRun and maintain regressions across various platforms including Simulation, Emulation, FPGA’s and track bug trends and verification progress metrics\nParticipate in microarchitecture, RTL, and verification reviews and write technical documentation\nWhat we're looking for\nBachelor's or Master's degree (or near-term graduation) in Electrical Engineering, Computer Engineering, Computer Science or a related field.\nStrong foundation in computer architecture and digital design, with solid understanding of at least two of the following:Out-of-order execution\nCPU front-end / control logic\nLoad/store and memory systems\nCache hierarchy and coherency\nVirtual memory\nFloating-point / computer arithmetic\nSIMD / vector processing\n\nWorking knowledge of a modern ISA including familiarity with ISA simulators or reference models\nProficiency in SystemVerilog, C/C++, assembly\nScripting experience for automation, test generation, regression management, or data analysis, such as Python, Tcl, or Rust\nWhat you'll do\nDevelop verification plans for the CPU core and cache hierarchy\nWrite and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block or subsystem\nBuild tests, scoreboards, and reference models, and close functional and code coverage\nTriage and root-cause failures with RTL designers and drive bugs to resolution\nParticipate in design and verification reviews and document your verification environment and results\nVerify the core against an ISA reference model using random instruction generation and co-simulation\nWhat we're looking for\nBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field\nRecently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification\nFamiliarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory\nHands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage\nUnderstanding of the end-to-end ASIC design flow and general VLSI concepts\nScripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus","description_format":"text","description_chars":3317,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-28T14:14:05Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2","filings_12m":2,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":222500,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":2}],"liveness":{"score":50,"band":"ok","label":"Likely open","p_open":1,"p_active":0.672,"p_room":0.75,"age_days":23,"expected_fill_days":24,"reasons":["conf:3","win:late"],"computed_at":"2026-10-29T05:49:05Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/rosaiclabs-cpu-design-verification-engineer-full-time","json_url":"https://alion.io/job/rosaiclabs-cpu-design-verification-engineer-full-time.json","meta":{"generated_at":"2026-10-29T20:08:14Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":29969,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-30T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4483163},"rest":"https://alion.io/mcp/rest/get_company?id=4483163"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Frosaiclabs-cpu-design-verification-engineer-full-time"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Frosaiclabs-cpu-design-verification-engineer-full-time"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Frosaiclabs-cpu-design-verification-engineer-full-time"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/rosaiclabs-cpu-design-verification-engineer-full-time\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Frosaiclabs-cpu-design-verification-engineer-full-time"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3400320}},{"tool":"search_jobs","arguments":{"company":"rosaiclabs.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3400320},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); 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