{"id":3400315,"url":"https://alion.io/job/rosaiclabs-cpu-physical-design-engineer-full-time","title":"CPU Physical Design Engineer - Full Time","company":{"id":4483163,"name":"RosaicLabs","domain":"rosaiclabs.com","url":"https://alion.io/company/rosaiclabs","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Austin, United 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design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)\n\nDrive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure\n\nOwn static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff\n\nDebug and close timing, power, and DRC/LVS violations across corners and modes\n\nCollaborate with RTL design, DFT, verification, and package/system teams to co-optimize PPA (power, performance, area)\n\nDevelop and improve physical design flows, scripts, and methodologies to boost QoR and turnaround time\n\nParticipate in design reviews, correlate silicon results with pre-silicon predictions, and drive root-cause debug of PPA gaps\n\nWhat we're looking for\nMaster's degree in Electrical Engineering, Computer Engineering, or a related field\n\n5+ years of industry experience in CPU or high-performance ASIC physical design\n\nStrong understanding of CPU microarchitecture: pipelines, out-of-order execution, caches, branch prediction, and interconnect\n\nHands-on experience with gate-level design, including standard-cell logic design and clock/reset architecture\n\nWorking knowledge of transistor-level/custom circuit design for high-speed and low-power structures\n\nProven track record driving synthesis and place-and-route (P&R) to timing, power, and area closure on complex blocks\n\nSolid grasp of static timing analysis (STA), signal integrity, and physical verification (DRC/LVS)\n\nProficiency with industry-standard EDA tools for synthesis, P&R, and signoff (see Tools & Technologies)\n\nScripting proficiency in Tcl, Perl, or Python for flow automation\n\nStrong analytical and debugging skills, with the ability to work through cross-corner, cross-mode PPA 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