{"id":1207520,"url":"https://alion.io/job/rtx-principal-fpga-engineer","title":"Principal FPGA Engineer","company":{"id":1162,"name":"RTX","domain":"rtx.com","url":"https://alion.io/company/raytheon-technologies","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":100,"open_postings":64,"ghost_share":0,"stale_share":0,"repost_share":0.141,"time_to_fill_p50_days":12,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["McKinney, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":107500,"max":204500,"currency":"USD","period":"year","gross":null,"usd_annual":204500},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Vitis","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-09-24T00:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-01T06:46:21Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Date Posted:\n2026-09-24\n\nCountry:\nUnited States of America\n\nLocation:\nUS-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG\n\nPosition Role Type:\nOnsite\n\nU.S. Citizen, U.S. Person, or Immigration Status Requirements:\nThe ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance\n\nSecurity Clearance Type:\nDoD Clearance: Secret\n\nSecurity Clearance Status:\nActive and existing security clearance required after day 1At Raytheon, the foundation of everything we do is rooted in our values and a higher calling - to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.\nThe Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.\nWe are currently seeking a Principal Electrical Engineer, with strong technical leadership ability, to function as the Field Programmable Gate Array Lead.\nThis position is an onsite role, located in McKinney, TX.\nWhat you will do\nProvide full lifecycle support of production quality FPGA designs for all major vendors and device families including AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.\nGenerate FPGA designs for the following applications: gigabit and multigigabit transceiver (MGT) serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.\nTranslate system level requirements into FPGA requirements\nArchitect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)\nLead small teams of FPGA engineers and code in VHDL for reliability and maintainability\nVerify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage\nDefine schedules for FPGA tasking and drive execution to the planned budget and schedule.\nIdentify and manage project risks and opportunities.\nCreate complete documentation including requirements, verification plan, and user’s guides\nLead medium sized teams to success.\nCoach, review, and delegate work to junior engineers.\nServe as a subject-matter expert within discipline.\nLead internal and external technical reviews.\nSupport customer interactions and relations.\nContribute to product and technology roadmaps\nMake improvements to processes, systems or products to enhance overall performance\nEngage in personal technical growth and facilitate technical growth in peers and junior engineers.\nQualifications You Must Have\nTypically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience.\nExperience to include one or more of the following:FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)\nExperience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.\nHands on experience with integration and debug of FPGA/ASIC in a lab environment\nExperience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.\nExperience with source code management, design reviews, and code release in a team development environment.\n\nQualifications We Value\nOne or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience.\nFPGA/ASIC design experience in one or more of the following areas:Radar processing techniques\nImage processing techniques for visual and infrared sensors\nEmbedded systems design using ARM, Microblaze, or NIOS processors\nGigabit serial interfaces and multi-gigabit transceivers (MGTs)\nConstrained random verification in UVM using System Verilog\nVerification utilizing emulation platforms, such as Veloce\nExperience with High Level Synthesis (HLS)\nExperience with vector processors and/or GPUs\nUsing AI to improve FPGA workflows (verification automation, log triage, regression analytics)\nAI/ML inference on FPGA (Vitis AI, FINN, custom accelerators)\n\nDemonstrated ability to lead successful teams.\nExperience managing technical, cost, and schedule risks and opportunities.\nExperience with project management tools such as Earned Value and/or Agile Execution.\nExperience communicating and documenting technical topics and presenting to customers and management.\nExperience leading a program transition from development to production.\nProposal development experience.\nExperience with intellectual property generation (patents & publications).\nDemonstrated mentorship of junior engineers.\nWhat We Offer\nOur values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.\nThis position offers relocation based on candidate eligibility.\nLearn More & Apply Now!\nThis position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website\nhere: https://www.state.gov/m/ds/clearances/c10978.htm\ngov/m/ds/clearances/c10978.htm\nNorth Texas: https://careers.rtx.com/global/en/raytheon-north-texas-location\nAs part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.\nThe salary range for this role is 107,500 USD - 204,500 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills.Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement.Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance.This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.\nPrivacy Policy and Terms:\nClick on this link to read the Policy and Terms","description_format":"text","description_chars":8509,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Flexible schedule","Life insurance","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":true,"industries":["Manufacturing","Space & Aerospace","Aerospace Manufacturing","Defense Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-25T00:53:08Z"}],"liveness":{"score":70,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.774,"p_room":0.9,"age_days":7,"expected_fill_days":12,"reasons":["conf:7","velocity","win:mid","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":{"stated_usd_annual":204500,"is_top_pay":false},"html_url":"https://alion.io/job/rtx-principal-fpga-engineer","json_url":"https://alion.io/job/rtx-principal-fpga-engineer.json","meta":{"generated_at":"2026-10-01T19:34:26Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2203,"day_limit":5000,"remaining_today":2797,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}