{"id":2550247,"url":"https://alion.io/job/saaz-fpga-design-engineer","title":"FPGA Design Engineer","company":{"id":4390064,"name":"Saaz","domain":"saaz.com","url":"https://alion.io/company/saaz","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"BambooHR","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Camarillo, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":92000,"max_usd":209000,"period":"year","method":"role_country_seniority_unknown","sample_n":2687},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-08-12T00:00:00Z","employer_posted_date":"2026-08-12","last_verified_at":"2026-10-17T16:05:39Z","board_verified":true,"closed_at":null,"days_open":66,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":66},"description":"SAAZ Micro is seeking a talented camera Firmware Engineer for the design, development, integration, and validation of embedded firmware for advanced visible, SWIR, MWIR, and LWIR imaging systems. This role bridges image sensor hardware, FPGA logic, camera electronics, and application software to deliver high-performance imaging solutions for commercial, aerospace, defense, and scientific applications.\nThe ideal candidate has strong experience with embedded systems, camera interfaces, real-time firmware development, and hardware bring-up.\nKey Responsibilities:\nDevelop and implement FPGA firmware (VHDL or Verilog) for image sensor control, high-speed data acquisition, synchronization, and real-time processing.\nInterface directly with visible and infrared (SWIR, MWIR, LWIR) sensors, including custom ROICs and commercial CMOS sensors.\nDesign and manage high-speed interfaces such as LVDS, MIPI CSI-2, Camera Link, USB 3.0, 10G Ethernet, or similar.\nCollaborate with image sensor engineers, system architects, and software teams to define sensor readout sequences, timing control, and data pipelines.\nBring up new hardware in the lab, including test and debug using oscilloscopes, logic analyzers, and protocol analyzers.\nDocument designs, interface specifications, and participatein hardware validation and production support.\nRequiredQualifications:\nB.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.\n5+ years of experience in camera system design or embedded hardware engineering.\nProven expertisein:\nFPGA development using VHDL or Verilog (AMD/Xilinx or Intel/Altera toolchains)\nHigh-speed signal design and layout for imaging or data acquisition systems.\nExperience interfacing with visible and IR image sensors\nFamiliarity with Git version control.\nExcellent analytical and troubleshooting skills.\nDesired Qualifications:\nFamiliarity with sensor timing, synchronization, and real-time video streaming.\nExperience optimizingimage acquisition pipelines.\nExperience implementing image correction algorithms.\nFamiliarity with secure boot and firmware update mechanisms.\nExperience with Python for automation and testing.\nFamiliarity with:\nGigE Vision \nGenICam\nUSB3 Vision \nCamera Link \nCoaXPress\nSuccess Metrics:\nFirmware compiles without critical warnings.\nCPU utilizationand memory usage meet design goals.\nCommunication interfaces (SPI, I²C, USB, Ethernet, etc.) achieve required throughput.\nCompliance with coding standards\nUnit and integration tests successfully completed.","description_format":"text","description_chars":2516,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-14T17:47:55Z"}],"visa":[],"liveness":{"score":16,"band":"cold","label":"Long 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