{"id":3700055,"url":"https://alion.io/job/salience-labs-physical-verification-engineer","title":"Physical Verification Engineer","company":{"id":2029320,"name":"Salience Labs","domain":"saliencelabs.ai","url":"https://alion.io/company/saliencelabs","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Oxford, United Kingdom"],"countries":["GB"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-11-03T14:41:49Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-08T04:39:58Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"About us\nSalience Labs is building an industry-defining approach to optical circuit switching for AI infrastructure, engineered for real latency reduction and cost savings. We're moving towards real-world deployment, and joining at this stage means genuine ownership over that next chapter, working alongside a highly technical team on one of the most consequential problems in AI infrastructure today.\nAbout the Role\nWe’re looking for a Physical Verification Engineer to drive DRC/LVS signoff for our integrated circuit and photonic integrated circuit (PIC) designs. You’ll work at the intersection of electronic and photonic design, running and debugging verification flows against foundry PDKs and helping keep our tapeouts clean.\nWhat You’ll Do\nRun and debug physical verification (DRC, LVS, extraction) on IC and photonic IC layouts\n\nDebug LVS/DRC discrepancies, including port mismatches, hierarchy mismatches, and device recognition issues\n\nRead, manipulate, and QA GDS/OASIS layout data\n\nMaintain and extend verification runsets and rule decks\n\nBuild Python/Tcl/shell tooling to automate verification flows and triage error reports\n\nMaintain verification libraries and runsets under version control, with controlled release processes\n\nHandle third-party and foundry IP with care, following licensing terms\n\nWork with design, layout, and CAD teams to close out verification issues ahead of tapeout\n\nDocument known issues, workarounds, and runset changes\n\nWhat You Bring\nRequired\n3+ years of hands-on physical verification experience in IC design\n\nPractical experience with Siemens Calibre and/or Synopsys ICV for DRC/LVS signoff\n\nExperience with custom/analog layout tools such as Cadence Virtuoso or Synopsys CustomCompiler\n\nStrong working knowledge of GDS/OASIS formats and LVS concepts\n\nProficiency with Linux and scripting in Python, Tcl, or shell\n\nExperience managing rule decks, runsets, or libraries under version control (e.g., Git)\n\nAbility to independently debug complex hierarchical netlist and layout issues\n\nStrong written communication for documenting root causes and fixes\n\nNice to have\nPhotonic IC verification experience\n\nExperience with Verilog/SystemVerilog netlists\n\nExposure to foundry PDK qualification\n\nExperience building internal automation to scale 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