{"id":129101,"url":"https://alion.io/job/sambanova-systems-principal-design-verification-engineer","title":"Principal Design Verification Engineer","company":{"id":100,"name":"SambaNova Systems","domain":"sambanova.ai","url":"https://alion.io/company/sambanova","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":13,"ghost_share":0,"stale_share":0.769,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":180000,"max":255000,"currency":"USD","period":"year","gross":null,"usd_annual":255000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"C++","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Claude","optional":true},{"name":"Formal Verification","optional":true}],"status":"closed","first_seen_at":"2026-08-17T18:39:57Z","employer_posted_date":"2026-09-07","last_verified_at":"2026-10-19T21:53:18Z","board_verified":false,"closed_at":"2026-10-19T21:53:18Z","days_open":63,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":63},"description":"SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) - a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.\nAbout the team\nSambaNova's RDU is the processor behind our inference systems, and design verification ensures quality and reliability before production. The team owns verification for block, full-chip, and gate-level benches, performance verification, coverage closure, and the emulation and FPGA prototypes.\nAbout the role\nSambaNova is looking for a Principal Design Verification Engineer to own verification for our next-generation RDU, the reconfigurable dataflow silicon behind our machine learning and AI systems. This is a senior individual-contributor role where you'll own the test plan, testbench architecture, coverage model, and sign-off criteria, while shaping the team-wide infrastructure, reuse patterns, and verification practices.\nYou'll work alongside principal engineers from the design, architecture, compiler, and runtime teams who have built and evolved this verification environment across several generations of silicon, to verify the chip against production ML workloads.\nResponsibilities\nSome of your responsibilities will include...\nOwn verification end to end for a major subsystem of the RDU: test plan, testbench architecture, coverage model, and sign-off criteria\nBuild the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out\nDevelop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level\nServe as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures\nOwn regression health and failure triage for your area: drive root cause, not just reproduction\nVerify functional and performance behavior\nAdvance DV methodology beyond your own area: reusable infrastructure, verification IP integration, and AI-assisted verification workflows the rest of the team adopts\nContribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab\nSet the technical bar through design and DV reviews, and mentor engineers to raise the level of the team's verification practice\nRequired qualifications\nBS or MS in EE, CS, or CE with 7+ years (or equivalent) of industry experience in ASIC design verification\nDeep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++\nFull-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure\nExperience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC\nTrack record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause\nDemonstrated technical leadership without formal authority: setting direction in reviews, arbitrating testbench decisions, and mentoring engineers\nWorking knowledge of modern computer architecture and of machine learning accelerators or SoCs\nPreferred qualifications\nMS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification\nDepth in high-speed I/O verification: protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR\nPerformance verification methodology: building performance benches and analyzing results, not only functional correctness\nFormal verification and assertion-based methods\nExperience evaluating, integrating, and validating third-party verification IP\nGate-level simulation and debug\nEmulation and FPGA prototyping platforms\nPost-silicon lab bring-up and functional validation, debugging first-silicon issues to root cause\nStrong understanding of one or more of computation, interconnect, or memory systems\nFluency with Claude or other AI tools applied to verification and flow development\n\nBase Salary Range:\nBase Pay Range\n$180,000—$255,000 USD\nSubmission Guidelines\n Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. \nEEO Policy\n SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.\nBenefits Summary for US-Based, Full-Time Employment Positions\nSambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.","description_format":"text","description_chars":5962,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity","Health insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-17T18:39:57Z"},{"event":"close","at":"2026-10-19T21:53:18Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 23 · green card filings: 30","filings_12m":23,"filings_prev_12m":34,"green_card_filings_12m":30,"median_offered_wage_usd":182500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":6}],"liveness":null,"pay":{"stated_usd_annual":255000,"is_top_pay":true},"html_url":"https://alion.io/job/sambanova-systems-principal-design-verification-engineer","json_url":"https://alion.io/job/sambanova-systems-principal-design-verification-engineer.json","meta":{"generated_at":"2026-10-20T16:54:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19205,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":100},"rest":"https://alion.io/mcp/rest/get_company?id=100"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsambanova-systems-principal-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsambanova-systems-principal-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsambanova-systems-principal-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sambanova-systems-principal-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsambanova-systems-principal-design-verification-engineer"}]}