{"id":129099,"url":"https://alion.io/job/sambanova-systems-senior-hardware-design-engineer","title":"Senior Hardware Design Engineer","company":{"id":100,"name":"SambaNova Systems","domain":"sambanova.ai","url":"https://alion.io/company/sambanova","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":79,"open_postings":13,"ghost_share":0,"stale_share":0.846,"repost_share":0,"time_to_fill_p50_days":40,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":120000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-08-18T13:16:56Z","employer_posted_date":"2026-09-07","last_verified_at":"2026-10-19T21:53:18Z","board_verified":true,"closed_at":null,"days_open":62,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":62},"description":"SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) - a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.\nAbout the team\ndiv]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8\">\n_*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown\">\nThe hardware design team writes the RTL for SambaNova's RDU, the processor behind our AI workload acceleration systems, covering the compute, memory, and networking subsystems. Engineers own specific blocks inside a larger subsystem, working alongside the principal engineers and architects who set its direction. A block stays with the engineer who wrote it through PPA closure, tapeout, and bring-up, so you debug your own design in silicon.\nAbout the role\nSambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work alongside principal engineers, architects, design verification engineers, and physical design engineers to implement innovative features in hardware that provide unique value to SambaNova.\nIn this role you will take ownership of blocks within a larger subsystem - contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tapeout, and silicon bring-up. You will grow your scope over time as you build depth in our architecture.\nThis role is onsite, based in either our San Jose, CA or Austin, TX office.\nResponsibilities\nSome of your responsibilities will include...\nWork with principal engineers and architects to author sections of the microarchitecture specification for compute, memory, or networking subsystems.\nCode, integrate, and debug SystemVerilog RTL for assigned blocks through the chip implementation and production lifecycle.\nMeet Power, Performance, and Area (PPA) targets for your blocks using advanced digital design techniques for high-speed design.\nPartner with design verification and physical design engineers to converge on functionality, timing, and area.\nImplement SystemVerilog Assertions (SVA) and run lint, CDC, and LEC flows to check design intent and keep blocks clean.\nParticipate in design reviews, presenting your design decisions and incorporating feedback.\nSupport post-silicon bring-up and debug for the blocks you own.\nContribute to design flow improvements, including AI and automation in EDA tool methodologies.\nRequired qualifications\nMaster's degree in Computer Engineering or Electrical Engineering with 3-5 years of relevant experience, or Bachelor's degree with 5-7 years.\nSolid foundation in computer architecture and digital logic design.\nStrong SystemVerilog RTL design skills for high-speed, high-performance ASICs.\nExperience making design decisions that trade off Power, Performance, and Area (PPA).\nWorking knowledge of industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).\nExperience with digital logic synthesis tools and Static Timing Analysis (STA).\nProficiency with industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).\nExperience implementing SystemVerilog Assertions (SVA) to check design intent.\nFamiliarity with tools and simulators for hardware performance analysis and tuning.\nFamiliarity with Git for managing release cycles.\nScripting skills in Python and Linux shell.\nAbility to work onsite in San Jose, CA or Austin, TX.\nPreferred qualifications\nExposure to a full ASIC development cycle through tapeout and production silicon.\nInterest in or knowledge of AI workload acceleration techniques.\nExperience with low-power design techniques (clock gating, DVFS) at advanced process nodes.\nExposure to emulation or FPGA prototyping platforms for pre-silicon validation.\n\nBase Salary Range:\nBase Pay Range\n$120,000—$200,000 USD\nSubmission Guidelines\n Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. \nEEO Policy\n SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.\nBenefits Summary for US-Based, Full-Time Employment Positions\nSambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.","description_format":"text","description_chars":6304,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Health insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-18T13:16:56Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 23 · green card filings: 30","filings_12m":23,"filings_prev_12m":34,"green_card_filings_12m":30,"median_offered_wage_usd":182500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":6}],"liveness":{"score":22,"band":"cold","label":"Long shot","p_open":1,"p_active":0.493,"p_room":0.45,"age_days":61,"expected_fill_days":40,"reasons":["conf:3","stale_co","velocity","win:tail"],"computed_at":"2026-10-19T05:45:15Z"},"pay":{"stated_usd_annual":200000,"is_top_pay":true},"html_url":"https://alion.io/job/sambanova-systems-senior-hardware-design-engineer","json_url":"https://alion.io/job/sambanova-systems-senior-hardware-design-engineer.json","meta":{"generated_at":"2026-10-20T01:29:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1781,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":100},"rest":"https://alion.io/mcp/rest/get_company?id=100"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsambanova-systems-senior-hardware-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsambanova-systems-senior-hardware-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsambanova-systems-senior-hardware-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sambanova-systems-senior-hardware-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsambanova-systems-senior-hardware-design-engineer"}]}