{"id":3831918,"url":"https://alion.io/job/samsung-electronics-hw-verification-engineering-lead-2","title":"HW Verification Engineering Lead","company":{"id":166,"name":"Samsung Electronics","domain":"samsung.com","url":"https://alion.io/company/samsung","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":140,"ghost_share":0.007,"stale_share":0.543,"repost_share":0.057,"time_to_fill_p50_days":36,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Claude","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-05T19:35:30Z","employer_posted_date":null,"last_verified_at":"2026-11-05T19:35:30Z","board_verified":false,"closed_at":null,"days_open":3,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":3},"description":"Job description:\n\nDesign, development, and verification of H/W IP for camera, multimedia, and display pipelines in smartphones.\n\nRole and Responsibilities:\n\nAs the lead of IP Verification / Pre-Silicon Validation, you will head a team responsible for the verification of our next generation purpose-specific custom HW IP. This critical role spans both in-house IP development as well as strategic evaluation, integration, and validation of various other IP blocks. You will bridge the gap between technical execution and people mentorship, ensuring delivery, high quality, high performance, and power-efficient hardware IPs that drive and differentiate our product line over competitors.\n\nSkills and Qualifications:\nOversee the end-to-end IP lifecycle and advanced verification\nEnsure robust validation methods are utilized to ensure zero-bug silicon\nDefine and implement best-in-class engineering practices, checklists, and design flows to maximize efficiency\nVerification / Emulation\nUnderstanding of digital design principles, algorithm, design, and architecture specifications\nUnderstanding of SystemC, C, and Python programming\nDesign direction in terms of performance, gate count, and power for various digital designs\nProficient in SystemVerilog/UVM/OVM\nFPGA IP/Custom ASIC prototyping and validation\nDeveloping scalable test benches in SystemVerilog and UVM\nUnderstanding of camera / multimedia / display / NPU subsystems in detail\nProven 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