{"id":3379980,"url":"https://alion.io/job/semtech-associate-engineer-physical-design","title":"Associate Engineer, Physical Design","company":{"id":58922,"name":"Semtech","domain":"semtech.com","url":"https://alion.io/company/semtech","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":19,"ghost_share":0,"stale_share":0.632,"repost_share":0,"time_to_fill_p50_days":47,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Aguascalientes, Mexico"],"countries":["MX"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":47000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":12},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verification & Validation","optional":false}],"status":"live","first_seen_at":"2026-10-27T00:00:00Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-30T20:39:04Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"ASIC/Layout Design Engineer 1\nPosition Summary: The ASIC/Layout Design Engineer 1 position is responsible for performing basic physical design and layout activities within\nour semiconductor company. This position supports ASIC layout development, assists with physical verification, and helps implement design components.\nThe role requires fundamental understanding of semiconductor layout principles, technical skills, and attention to detail to support the development of\nintegrated circuit physical designs in the complex semiconductor environment.\nKey Responsibilities:\nLayout Design Support (30%):\nSupport physical layout of standard cells, memory blocks, and basic circuit elements\nAssist with implementation of layout designs based on schematics and specifications\nHelp with placement and routing of components and interconnects\nSupport floorplanning and power distribution network development\nMaintain layout documentation and design files Physical Verification Support (25%):\nAssist with design rule checking (DRC) and layout vs. schematic (LVS) verification\nSupport resolution of basic physical verification issues\nHelp with design rule violations identification and correction\nParticipate in verification run setup and execution\nDocument verification results and issue resolutions Layout Data Preparation (15%):\nSupport preparation of layout data for manufacturing\nAssist with design for manufacturing (DFM) checks and optimizations\nHelp with mask data preparation and file generation\nSupport tape-out activities and data transfer\nMaintain design databases and version control Design Tool Support (10%):\nSupport physical design tools and EDA environments\nAssist with design kit implementation and updates\nHelp maintain layout libraries and technology files\nSupport design flow execution and automation\nAssist with tool setup and configuration Technology Migration Support (10%):\nAssist with layout migration between technology nodes\nSupport porting of designs to new process technologies\nHelp implement technology-specific design rules and constraints\nParticipate in migration verification and validation\nDocument process differences and layout adjustments Technical Learning and Development (10%):\nDevelop understanding of physical design principles and methodologies\nLearn semiconductor manufacturing processes and design rules\nSupport implementation of layout best practices\nParticipate in technical training and development activities\nIncrease knowledge of semiconductor technologies and physical design approaches\nEducation and Experience:\nBachelor's degree in Electrical Engineering, Computer Engineering, or related technical field\n0-2 years of experience in ASIC layout, physical design, or related role\nBasic knowledge of semiconductor design and layout principles\nExperience with EDA tools and design environments\nFamiliarity with IC layout verification preferred\nQualifications:\nBasic knowledge of ASIC physical design principles and layout methodologies\nTechnical understanding of semiconductor manufacturing processes and design rules\nProficiency with physical design tools, verification software, and layout environments\nAttention to detail and accuracy in layout implementation\nGood organizational and time management skills\nEffective written and verbal technical communication abilities\nBasic problem-solving capabilities\nUnderstanding of schematic-to-layout correspondence and verification\nAbility to read and interpret design specifications and technical documentation\nWillingness to learn and develop physical design expertise\nBasic understanding of semiconductor devices and circuit operation a plus\nTravel Requirements:\nMinimal travel required (less than 5% of time)\nMay require occasional travel between company facilities\nLevel of Authority:\nPerforms routine physical design tasks following established procedures\nMakes basic decisions regarding layout implementation and verification\nEscalates technical issues and design challenges to appropriate personnel\nWorks under supervision with limited independent decision-making\nFollows established policies and procedures for physical design activities\nJob Complexity:\nPerforms routine physical design activities with clear guidelines and procedures\nSupports established layouts with defined parameters and specifications\nWorks with standard layout components and structures\nRequires understanding of basic physical design concepts and semiconductor principles\nExpected to maintain accuracy while implementing layouts and running verifications\nWorks with various engineering stakeholders on design projects\nLearns to identify layout issues and escalate appropriately","description_format":"text","description_chars":4646,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Energy & Utilities","Farming & Agriculture","RF & Wireless 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