{"id":3434840,"url":"https://alion.io/job/semtech-sr-engineer-process-development","title":"Sr. Engineer, Process Development","company":{"id":58922,"name":"Semtech","domain":"semtech.com","url":"https://alion.io/company/semtech","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":19,"ghost_share":0,"stale_share":0.947,"repost_share":0,"time_to_fill_p50_days":47,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["City of Industry, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":95000,"max":135000,"currency":"USD","period":"year","gross":null,"usd_annual":135000},"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"CVD","optional":false},{"name":"Design of Experiments","optional":false},{"name":"Ellipsometry","optional":false},{"name":"FMEA","optional":false},{"name":"JMP","optional":false},{"name":"Minitab","optional":false},{"name":"Photolithography","optional":false},{"name":"Plasma Etch","optional":false},{"name":"Python","optional":false},{"name":"Statistical Process Control","optional":false}],"status":"live","first_seen_at":"2026-10-28T00:00:00Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-11-02T22:50:34Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Location: Rowland, CA (Onsite)\nPosition Summary\nThe Process Engineer is responsible for developing, optimizing, and sustaining wafer fabrication processes that support yield, quality, and throughput for InP photonic device lines, specifically InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips (GC). The Process Engineer owns one or more fab process modules (photolithography, PECVD, dry etch, wet etch, and metallization), including the Mesa etch and surface preparation steps that support MOCVD epitaxial regrowth of InP current-blocking layers used to form the buried heterostructure. This role applies advanced technical training in materials, semiconductor processing, and statistical methods to resolve process excursions, improve device performance and yield, and transition new processes into volume production.\nWorking in a III-V cleanroom environment with minimal supervision, the Process Engineer partners closely with Wafer Fab Supervisors, Technicians, Equipment Engineering, Device and Test Engineering, and Quality to maintain Process-of-Record (POR) discipline, drive data-based decisions, and support reliable, high-yield, high-volume manufacturing.\nResponsibilities:\nProcess Development & Module Ownership\nOwn assigned process modules (photolithography, PECVD, dry etch, wet etch, and/or metallization) for InP BH DFB laser and BH GC production, with responsibility for process capability, stability, and yield performance\nDevelop, characterize, and optimize processes such as lithography CD and overlay control, dielectric film properties, Mesa etch profile and depth control, surface preparation for MOCVD regrowth, and ohmic contact formation\nDefine process windows, specifications, and control limits using designed experiments and statistical analysis\nEvaluate new materials, chemistries, equipment, and process techniques to improve device performance, yield, throughput, and cost\nCharacterize process results using SEM, profilometry, ellipsometry, TLM, and device electrical and optical test data to link process parameters to device performance\nExcursion Response, Root Cause & Yield Improvement\nLead root-cause investigation and corrective action for process excursions, yield loss, and drift (e.g., CD shift, film stress or thickness non-uniformity, etch rate or profile drift, contact resistance shift)\nAnalyze in-line, wafer-level, and device-level data to identify yield detractors and prioritize improvement projects\nUse structured problem-solving methods (8D, fishbone, FMEA) and short-loop experiments to isolate root cause and verify corrective actions\nWork with Equipment Engineering to resolve tool-related issues and to qualify tools after maintenance or modification\nProcess Control, Documentation & Change Management\nDefine and review SPC charts, control limits, and monitor strategies for assigned process modules, and ensure out-of-control events are addressed in a timely manner\nAuthor and maintain POR documentation, process specifications, and work instructions for assigned process areas\nApprove and manage process changes through the change control system, including qualification and post-change verification of process stability\nProvide technical guidance, training, and process-specific direction to Wafer Fab Supervisors, Technicians, and Operators\nNPI, DOE & Cross-Functional Support\nPlan and execute DOEs, process qualifications, and NPI process runs, and transition new or modified processes into volume production\nPartner with Device Engineering, MOCVD/Epitaxy, Test, Quality, and Production Planning to align process capability with product requirements and customer commitments\nPrepare technical reports, data summaries, and presentations for fab management and cross-functional teams\nSupport customer and supplier technical reviews, audits, and failure analysis activities as needed\nMinimum Qualifications:\nMaster’s degree in materials science, electrical engineering, chemical engineering, physics, or a related engineering or science field required\n2 - 5 years of experience in semiconductor/photonics wafer processing, with direct III-V/InP process experience preferred; relevant graduate research in III-V device fabrication will be considered toward experience\nHands-on experience with one or more of the following process areas: photolithography, PECVD, dry etch, wet etch, and metallization\nExperience with InP-based laser or photonic integrated circuit fabrication preferred\nStrong working knowledge of semiconductor process physics and chemistry, including lithography, thin film deposition, plasma and wet etch, and metallization/ohmic contact formation for III-V materials\nProficiency in statistical analysis, SPC, and design of experiments (DOE) using tools such as JMP, Minitab, Python, or equivalent\nDemonstrated ability to independently lead root-cause investigations and drive corrective actions to closure\nAbility to correlate process data with device electrical and optical performance\nFamiliarity with fab metrology and characterization tools (CD-SEM, profilometer, ellipsometer, XRD, SEM, TLM test structures)\nStrong written and verbal communication skills, with the ability to present technical results to management and cross-functional teams\nAbility to work effectively with technicians, supervisors, and engineers in a team environment\nAbility to work in a cleanroom environment for extended periods across multiple process bays\nAbility to work around chemicals (acids, solvents), process gases, and precious metals with proper safety procedures\nMay require flexibility to support engineering runs or excursions outside standard shift hours\nThe intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.\nAll duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.\nA reasonable estimate of the pay range for this position is $95,000 - $135,000. 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