{"id":1842617,"url":"https://alion.io/job/semtech-sr-manager-verification","title":"Sr. Manager Verification","company":{"id":58922,"name":"Semtech","domain":"semtech.com","url":"https://alion.io/company/semtech","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":19,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-06T05:45:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":16000,"max_usd":40000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"CI/CD","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-03-10T00:00:00Z","employer_posted_date":"2026-03-10","last_verified_at":"2026-10-06T21:37:40Z","board_verified":true,"closed_at":null,"days_open":211,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":210},"description":"Responsibilities:\nLead, supervise, mentor, and develop a team of verification engineers across multiple projects. Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects. (20%)\n\nTrack & report verification progress using quantitative metrics and coverage analysis. Identify and mitigate verification risks early. Report to remote verification & design teams. Coordinate with project management and cross-functional teams. (20%)\n\nDrive definition and implementation of comprehensive verification plans and test strategies for digital/mixed-signal integrated circuit designs. Work closely with design teams to understand micro-architecture and functional specifications. Direct detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (20%)\n\nManage design and implementation of complex testbenches using System Verilog and UVM methodology. Lead block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (20%)\n\nInterface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)\n\nDrive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)\n\nTechnical support to silicon lab evaluation, test, product and application engineers. (5%)\n\nMinimum Qualifications:\n8+ years of industry experience in integrated circuit design verification (DV)\n\n3+ years in a technical leadership or management role\n\nB.S. or M.S. in Electrical or Computer Engineering\n\nProven track record of successful tape-outs for complex digital or mixed-signal designs\n\nDemonstration of ability to lead technical teams and drive high-quality & timely results\n\nExperience managing concurrent projects, competing priorities and sub-teams\n\nStrong analytical, synthesis and problem solving skills\n\nIn-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.\n\nProficiency in System Verilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens)\n\nExperience with standard hardware protocols (I2C, I3C, SPI, MIPI)\n\nIndependent, self-motivated, rigorous, innovating, team player and able to follow through\n\nExcellent verbal and written communication skills\n\nDesired Qualifications\nKnowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application\n\nExperience with analog block behavioral modelling with SV RNM/Verilog/VHDL\n\nExperience with consumer and/or ITA market circuit developments","description_format":"text","description_chars":3373,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-04T18:22:40Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long shot","p_open":1,"p_active":0.153,"p_room":0.28,"age_days":210,"expected_fill_days":30,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-06T05:45:30Z"},"pay":null,"html_url":"https://alion.io/job/semtech-sr-manager-verification","json_url":"https://alion.io/job/semtech-sr-manager-verification.json","meta":{"generated_at":"2026-10-07T00:34:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":979,"day_limit":5000,"remaining_today":4021,"minute_limit":60,"resets_at":"2026-10-08T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58922},"rest":"https://alion.io/mcp/rest/get_company?id=58922"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsemtech-sr-manager-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsemtech-sr-manager-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsemtech-sr-manager-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/semtech-sr-manager-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsemtech-sr-manager-verification"}]}