{"id":2827136,"url":"https://alion.io/job/siemens-design-verification-engineer","title":"Design Verification Engineer","company":{"id":131,"name":"Siemens","domain":"siemens.com","url":"https://alion.io/company/siemens","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":12,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":23900,"max":47800,"currency":"USD","period":"year","gross":null,"usd_annual":47800},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"SystemC","optional":true}],"status":"live","first_seen_at":"2026-10-18T23:40:57Z","employer_posted_date":"2026-10-18","last_verified_at":"2026-10-23T13:34:31Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Siemens Digital Industries Software - Where today meets tomorrow.\nLet's make the difference together!\nMeet the team - Video\nSiemens Digital Industries (DI) is an innovation leader in automation and digitalization. Closely, collaborating with partners and customers, we care about the digital transformation in the process and discrete industries. With our Digital Enterprise portfolio, we provide and encourage companies of all sizes with an end-to-end set of products, solutions and services to integrate and digitalize the entire value chain. Meaningful optimization for the specific needs of each industry, our outstanding portfolio supports customers to achieve greater efficiency and flexibility. We are constantly adding innovations to its portfolio to integrate groundbreaking future technologies. We have our global headquarters in Nuremberg, Germany, and have around 75,000 employees internationally.\nWe offer a role with responsibility, independence and the possibility to contribute proactive. We foster a teamwork culture with room for individual development\nPlease visit https://siemensneo.com/disw/\nHAV Solutions R&D Group in Cairo, Egypt is looking for Senior Design Verification Engineer (Full-time Position) to join Storage Solutions R&D Team.\nMain Responsibilities:\nThe job includes - but not limited to - the following responsibilities:\nDevelop and execute verification plans, including testbench architecture and test cases development.\nDesigning and developing co-emulation-based and/or simulation-based verification environments.\nWorking on already existing complex testbenches targets different platforms (simulation/co-emulation).\nIntegrating Software and Hardware DUTs and dealing with different programming with the verification environment.\nImplement and monitor code coverage and/or functional coverage metrics to assess verification completeness.\nRunning and debugging complete testbenches composed of embedded software and hardware components on Questa and/or Veloce platforms.\nWork closely with design and architecture teams to understand the design specifications and requirements.\nIdentify and debug issues in the design and verification environment.\nCollaborate with design team to identify and resolve coverage gaps.\nMentor junior engineers and provide guidance on best practices in verification.\nDocument and report verification progress and coverage status to stakeholders.\nJob Requirements:\nB.Sc. or M.Sc. in Computer/Electronics and Communication Engineering with experiencing in H/W design verification field.\nAdvanced knowledge in SystemVerilog for creating testbenches and writing assertions.\nAdvanced knowledge in UVM (Universal Verification Methodology) for building re-usable verification environments.\nGood knowledge of code coverage and/or functional coverage techniques.\nGood knowledge of integrating commercial VIP in UVM testbenches.\nGood knowledge of RTL development / Verilog.\nGood knowledge of digital circuits, digital design/systems and computer architecture.\nFamiliarity with Siemens EDA tools and solutions.\nKnowledge of C, C++, OOP.\nKnowledge of scripting languages (Perl, Shell, TCL).\nExcellent command of English language.\nAbility to work independently and as part of a team.\nExcellent presentation and communication skills.\nKnowledge of storage protocol standards (UFS, USB, SAS, SATA, …) is a plus.\nKnowledge of programming using SystemC is a plus.\nOur Benefits & Rewards\nThe salary range for this position is $23,900 to $47,800 and this role is eligible to earn incentive compensation. The actual compensation offered is based on the successful candidate's job-related skills, experience, and relevant education/training. Siemens offers health and wellness benefits to employees; you can access the benefits available in your country via the link: https://jobs.sw.siemens.com/benefits/\nWe value your unique identity and perspective. We are fully committed to providing equitable opportunities and building a workplace that reflects the diversity of society, while ensuring that we attract the best talent based on qualifications, skills, and experiences.\nWorking at Siemens Software\nWhy us?\nWorking at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.\nAt Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow‘s reality.\nSiemens Industry Software is an equal opportunities employer and does not discriminate unlawfully on the grounds of age, disability, gender assignment, marriage, and civil partnership, pregnancy and maternity, race, religion or belief, sex, sexual orientation, or trade union membership.\nSiemens. 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