{"id":3599544,"url":"https://alion.io/job/sifive-cpu-design-verification-engineer-ii","title":"CPU Design Verification Engineer II","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":20,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":93,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Git","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Cadence JasperGold","optional":true},{"name":"Synopsys VC Formal","optional":true}],"status":"live","first_seen_at":"2026-11-02T07:26:37Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-04T12:28:00Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nAbout the Role\nYou'll verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout. This is a hands-on role at the block and core level: you'll write testbench components, build constrained-random and directed stimulus, close coverage, and debug the hard failures that come out of nightly regressions - pipeline hazards, memory-ordering violations, speculation and flush corner cases, and co-simulation divergences between RTL and the golden ISA model.\nYou'll work directly with core micro-architects and RTL designers, and you'll own verification of specific units (e.g. rename/dispatch, issue queues, load-store unit, MMU/TLB, branch prediction, or the retire/commit path) as well as core-level scenarios.\nWhat You'll Do\nOwn the verification plan for one or more OOO core units: extract testable features from the micro-architecture spec, define stimulus and coverage requirements, and drive them to closure.\nBuild and extend UVM testbench infrastructure - agents, drivers/monitors, scoreboards, reference models, functional coverage, and assertions (SVA).\nDevelop constrained-random test generators and directed tests (C/assembly test programs plus SV stimulus) targeting deep pipeline states: speculative execution and misprediction recovery, replay and livelock scenarios, exception/interrupt injection, memory-ordering and coherence corner cases, and privilege/virtual-memory transitions.\nDebug regression failures end to end: triage waveforms, correlate RTL state against instruction-by-instruction co-simulation mismatches (PC, write-data, CSR state), and reduce failures to a minimal reproducer with a clear root-cause writeup for the designer.\nDrive coverage closure - code, functional, and assertion coverage - including analyzing holes, adding stimulus or coverage waivers with justification, and reporting progress against tapeout milestones.\nMaintain and improve regression health: keep failure signatures triaged and bucketed, reduce noise, and improve turnaround time and debuggability of the test flow.\nContribute to the verification environment and tooling: build/run flows, log parsers, failure-signature classification, and CI integration.\nReview micro-architecture and RTL changes for verification impact; participate in spec reviews and file spec ambiguities.\nRequired Qualifications\nBS or MS in Electrical/Computer Engineering, Computer Science, or equivalent.\n2+ years of professional pre-silicon functional verification experience (MS with strong relevant internship/project experience considered).\nStrong SystemVerilog and UVM: you can write and extend testbench components independently, not just author tests in an existing environment.\nSolid computer-architecture fundamentals: pipelining, caches and cache hierarchy, branch prediction, register renaming, out-of-order issue and in-order retirement, memory consistency and coherence basics.\nProficiency with a simulator (VCS, Questa, or Xcelium) and waveform debug (Verdi, Visualizer, or similar) - including independently debugging a failing test from log to waveform to root cause.\nWorking knowledge of assembly and C at the bare-metal level; comfortable reading disassembly and reasoning about instruction streams.\nScripting for automation and analysis: Python, plus shell/Makefile fluency.\nVersion control and code review workflow (Git).\nPreferred Qualifications\nExperience verifying an out-of-order or superscalar core\nRISC-V experience: familiarity with the unprivileged and privileged specs, and with extensions such as vector (V), hypervisor (H), or atomics (A).\nExperience with ISA co-simulation / lockstep golden-model flows (spike or equivalent) and with debugging scoreboard mismatches.\nRandom instruction-stream test generators (e.g. Sting, RISCV-DV, force-riscv, or an in-house equivalent) - including constraining and extending a generator, not just running it.\nFormal property verification for control-logic blocks (JasperGold or VC Formal).\nExposure to memory-model verification, litmus tests, or a coherence/ordering checker.\nPerformance verification or performance-counter validation experience.\nEmulation/FPGA prototyping, or post-silicon bring-up exposure.\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. 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