{"id":56093,"url":"https://alion.io/job/sifive-principal-design-verification-engineer-cpu-coherent-interconnect","title":"Principal Design Verification Engineer – CPU Coherent Interconnect","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":76,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Boston, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231444,"max":282876,"currency":"USD","period":"year","gross":null,"usd_annual":282876},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-08-12T00:00:00Z","employer_posted_date":"2026-08-12","last_verified_at":"2026-10-19T04:04:47Z","board_verified":true,"closed_at":null,"days_open":68,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":68},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nAbout the Role\nSiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.\nThis is a principal tech-lead role for an engineer who can define architecture-aware verification strategy, identify risk early, solve complex subsystem-level problems, and raise verification quality across the broader interconnect verification effort.\nIn this role, you will work across architecture, RTL, formal, performance, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, buffering behavior, arbitration, quality-of-service behavior, and subsystem integration across multiple interfaces and bridge paths.\nResponsibilities\nLead verification planning and execution for a cache-coherent interconnect subsystem from block level through subsystem integration and signoff.\nDefine verification strategy, test plans, closure criteria, assertions, checkers, scoreboards, stimulus approaches, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, arbitration, QoS, and error handling.\nDrive verification across interface boundaries, bridges, protocol adaptation layers, and related subsystem data-movement paths.\nDevelop high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic behavior.\nPartner closely with architecture, RTL, and formal teams to review specifications, close ambiguity early, and improve design debugability and verification completeness before issues harden late in the cycle.\nDrive efficient root-cause analysis across specification, RTL, assertions, test content, and verification infrastructure, and push issues to durable closure.\nApply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented verification where appropriate.\nInfluence methodology and infrastructure across the broader horizontal interconnect verification effort, not just the block directly assigned to you.\nMentor engineers and raise the technical bar through reviews, debug leadership, stronger verification practices, and reusable infrastructure.\nMinimum Qualifications\nBS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification, with depth appropriate for a Principal / T6 role.\nStrong hands-on experience with SystemVerilog-based verification and reusable verification infrastructure for complex hardware subsystems.\nStrong understanding of cache-coherent systems, on-chip interconnects, CPU memory-subsystem behavior, and verification of ordering, snooping, and flow-control semantics.\nDeep experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows for complex subsystem-level designs.\nStrong debug skills and the ability to translate architectural intent into effective verification strategy and execution.\nStrong software, scripting, and automation skills in Python or similar languages for scalable DV infrastructure and workflows.\nStrong technical communication and the ability to work effectively across architecture, RTL, formal, performance, and verification teams.\nPreferred Qualifications\nDirect experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance CPU or SoC environments.\nExperience with large subsystem integration challenges involving coherent traffic, ordering, arbitration, QoS, error handling, and bridge-heavy designs.\nExperience with memory consistency, weak ordering, and multicore coherency verification challenges.\nExperience with formal verification, emulation, or performance-oriented verification for complex subsystem signoff problems.\nDemonstrated technical leadership through mentoring engineers, influencing methodology, and driving cross-team execution on difficult verification efforts.\nWhat Success Looks Like\nVerification plans capture the real architectural and subsystem-level risks early and completely.\nDifficult coherent interconnect bugs are found early, debugged efficiently, and closed with durable fixes.\nVerification quality, methodology, and reusable infrastructure improve across the broader interconnect DV organization because of your contributions.\nArchitecture, design, and DV teams rely on this engineer as a technical leader for complex coherent interconnect verification challenges in high-performance CPU development.\nPay & Benefits\nConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\nBase Pay Range\n$231,444.00-$282,876.00In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.\nCalifornia residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.","description_format":"text","description_chars":8243,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Retirement plans"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-08-12T00:00:00Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6","filings_12m":6,"filings_prev_12m":10,"green_card_filings_12m":0,"median_offered_wage_usd":162500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":3}],"liveness":{"score":47,"band":"ok","label":"Likely open","p_open":1,"p_active":0.777,"p_room":0.6,"age_days":68,"expected_fill_days":76,"reasons":["conf:1","velocity","win:late","crowd:brand"],"computed_at":"2026-10-19T05:45:15Z"},"pay":{"stated_usd_annual":282876,"is_top_pay":true},"html_url":"https://alion.io/job/sifive-principal-design-verification-engineer-cpu-coherent-interconnect","json_url":"https://alion.io/job/sifive-principal-design-verification-engineer-cpu-coherent-interconnect.json","meta":{"generated_at":"2026-10-19T14:38:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10688,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58802},"rest":"https://alion.io/mcp/rest/get_company?id=58802"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsifive-principal-design-verification-engineer-cpu-coherent-interconnect"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsifive-principal-design-verification-engineer-cpu-coherent-interconnect"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsifive-principal-design-verification-engineer-cpu-coherent-interconnect"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sifive-principal-design-verification-engineer-cpu-coherent-interconnect\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsifive-principal-design-verification-engineer-cpu-coherent-interconnect"}]}