{"id":196273,"url":"https://alion.io/job/sifive-senior-design-verification-engineer-2","title":"Senior Design Verification Engineer","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":72,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":54000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Machine Learning","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-03T12:33:30Z","employer_posted_date":"2026-09-03","last_verified_at":"2026-10-20T12:01:15Z","board_verified":true,"closed_at":null,"days_open":46,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":46},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nRole Summary\nWe are seeking a Senior Design Verification Engineer to own block- and subsystem-level DV for advanced out-of-order (OoO) CPU cores. You will work closely with micro-architects and RTL designers to verify complex execution pipelines, memory systems, and coherence protocols using modern, coverage-driven methodologies.\nKey Responsibilities\nVerification Planning & Ownership\nDrive verification for key OoO CPU blocks, such as:\n\nFront-end: fetch, branch prediction, decode.\n\nRename and register mapping.\n\nIssue queues / schedulers and execution units.\n\nReorder buffer (ROB), retirement, exceptions, and flush/replay.\n\nLoad-store unit (LSU), store buffer, atomics/LR-SC, fences.\n\nL1 caches, TLBs, MMU interfaces, and coherence interfaces.\n\nDerive verification plans from architecture and micro-architecture specs, with emphasis on:\n\nSpeculative execution flows and pipeline hazards.\n\nMemory ordering / consistency model compliance.\n\nInteraction with cache hierarchy and coherence.\n\nTestbench & Environment Development\nDevelop and maintain SystemVerilog/UVM testbenches:\n\nUVM agents, monitors, scoreboards, reference models.\n\nConstrained-random stimulus and directed tests for OoO corner cases.\n\nImplement self-checking mechanisms for:\n\nInstruction retirement and architectural state.\n\nLSU / memory ordering, atomics, and fence behavior.\n\nTLB, page-table, and privilege/protection flows as needed.\n\nCoverage & Quality\nDefine and track functional, code, and assertion coverage; identify gaps and add tests/monitors to close them.\nCreate and maintain assertions (SVA) for key micro-architectural properties:\n\nNo deadlock/livelock in scheduler, ROB, LSQ.\n\nCorrect handling of mispredicts, exceptions, interrupts, and flush paths.\n\nCorrect data forwarding and hazard resolution in the pipeline.\n\nAnalyze regression results, triage failures, and drive issues to closure with design and architecture teams.\n\nDebug & Collaboration\nDebug complex failures in:\n\nSpeculation / replay (e.g., wrong-path side-effects, partial flushes).\n\nLoad-store ordering and memory consistency violations.\n\nTLB / MMU corner cases and privilege/protection issues.\n\nCollaborate with:\n\nMicro-architecture & RTL on fixes and design clarifications.\n\nPerformance / modeling teams to align micro-architectural behavior and verification scenarios.\n\nPost-silicon / validation teams to correlate pre- and post-silicon issues.\n\nMethodology & Mentoring\nContribute to DV methodology improvements (UVM components, coverage strategies, regression flows).\n\nProvide guidance and code reviews to junior engineers on testbench design, stimulus generation, and debug.\n\nRequired Qualifications\nEducation: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.\nExperience:\n\nTypically 5-10 years of ASIC/SoC/IP design verification experience.\n\nDirect experience verifying out-of-order or superscalar CPU cores (or closely related high-performance pipelines).\n\nTechnical Skills:\n\nStrong proficiency in System Verilog and UVM (or equivalent class-based DV methodology).\nSolid understanding of CPU micro-architecture, including:\n\nFetch/decode, rename, ROB, issue/execute, bypassing, commit.\n\nLSU, store buffer, atomics/LR-SC, fences, and memory ordering.\n\nL1 caches, TLBs, page-table walkers, and basic coherence concepts.\n\nHands-on experience with:\n\nConstrained-random and coverage-driven verification.\n\nWriting and debugging SVA assertions.\n\nIndustry-standard simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).\n\nSoft Skills:\n\nStrong problem-solving and debug skills on complex, corner-case bugs.\n\nEffective communication and teamwork across DV, design, and architecture.\n\nAbility to work independently on complex blocks while contributing to a larger project.\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. 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