{"id":108280,"url":"https://alion.io/job/sifive-senior-design-verification-infrastructure-engineer-vips-and-testbench","title":"Senior Design Verification Infrastructure Engineer - VIPs and Testbench","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":76,"computed_at":"2026-10-31T05:58:55Z"}},"role":"DevOps","role_family":"DevOps","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":57000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":53},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Chisel","optional":false},{"name":"CI/CD","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"Scala","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verification & Validation","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-07-09T00:00:00Z","employer_posted_date":"2026-07-09","last_verified_at":"2026-10-31T09:13:42Z","board_verified":true,"closed_at":null,"days_open":114,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":114},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nJoin SiFive’s Design Verification Infrastructure team to develop and maintain the Verification Platform VIPs, AIPs, and other testbench components used across SiFive. An ideal candidate will be a strong Design Verification engineer with a solid understanding of software engineering. You will be expected to collaborate with Design Verification engineers to develop reusable testbench components and integrate them within SiFive’s Chisel-based Verification Platform..\nResponsibilities:\nArchitect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities\n\nDevelop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators\n\nDevelop Verification Platform VIPs, AIPs, and other testbench components using System Verilog, UVM, and other related technologies\n\nDevelop Verification Platform test plans and testbenches to verify and release testbench components with high quality\n\nEducate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform\n\nRequirements:\nDesign Verification experience with System Verilog and UVM\n\nExperience designing and verifying VIPs, AIPs, and other testbench components\n\nUnderstanding of modern software engineering practices\n\nTypically 3+ years with BS/MS/PhD in EE/CE/CS or related field.\n\nDesired:\nExperience with Chisel, Scala, and/or Python\n\nUnderstanding of EDA tools and flows for Design Verification\n\nFamiliarity with DevOps practices, build systems, and CI / CD\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. 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