{"id":1397000,"url":"https://alion.io/job/sifive-senior-engineer-design-verification","title":"Senior Engineer - Design Verification","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":22,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":84,"computed_at":"2026-09-30T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ahmedabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":47000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-28T13:51:20Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-09-30T04:51:54Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nAbout the Role\nSiFive is looking for a Senior Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs.\nThis is a T3 / Senior Engineer individual-contributor role within the Interconnect horizontal area, focused on coherent interconnect and related subsystem behavior.\nIn this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across multiple interface types and bridge paths.\nWe are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the broader interconnect verification effort.\nResponsibilities\nUnderstand the coherent interconnect architecture and create effective verification strategies and test plans for the assigned area.\n\nDevelop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, and error handling.\n\nVerify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including conversion, buffering, deinterleaving, and related data-movement behavior.\n\nDefine and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, ordering, credits, arbitration, QoS behavior, and integration scenarios.\n\nAnalyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.\n\nCollaborate closely with architecture, design, formal, and software teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.\n\nWrite functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.\n\nContribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.\n\nMinimum Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n5+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in coherent interconnect, cache, memory-system, or CPU-subsystem verification.\n\nStrong hands-on experience with SystemVerilog and UVM-based verification.\n\nSolid understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, and verification of ordering and flow-control semantics.\n\nExperience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.\n\nExperience verifying protocol behavior such as ordering, backpressure, buffering, arbitration, flow control, and error handling.\n\nStrong debugging skills and the ability to root-cause issues across specification, RTL, and verification environment layers.\n\nStrong problem-solving skills and the ability to work effectively across architecture, design, and verification teams.\n\nPreferred Qualifications\nDirect experience verifying coherent interconnect, NoC, cache, or memory-subsystem functionality in multicore or high-performance SoCs.\n\nExperience with subsystem integration and protocol interactions across multiple interfaces or bridge paths.\n\nFamiliarity with one or more industry protocols such as AXI, CHI, ACE, CXL, UCIe, or similar high-performance interface standards.\n\nFamiliarity with scripting and automation using Python or similar languages.\n\nExperience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.\n\nExperience contributing reusable infrastructure or methodology improvements that benefit a broader DV team.\n\nWhat Success Looks Like\nVerification plans are complete and aligned with the highest architectural and protocol risks.\n\nCritical coherent-interconnect bugs are found early, debugged efficiently, and closed with durable fixes.\n\nCoverage and verification quality improve meaningfully under your ownership.\n\nThe coherent interconnect verification effort becomes more scalable, reusable, and predictable because of your contributions.\n\nDesign and architecture teams rely on you as a strong technical partner for difficult protocol, coherency, and integration problems.\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.","description_format":"text","description_chars":6432,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-28T13:51:20Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":84,"reasons":["conf:0","velocity","win:early","comp:brand"],"computed_at":"2026-09-30T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/sifive-senior-engineer-design-verification","json_url":"https://alion.io/job/sifive-senior-engineer-design-verification.json","meta":{"generated_at":"2026-10-01T02:03:45Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1672,"day_limit":5000,"remaining_today":3328,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}