{"id":3782990,"url":"https://alion.io/job/sifive-senior-rtl-design-engineer-cpu-frontend-2","title":"Senior RTL Design Engineer - CPU Frontend","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":19,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":94,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cambridge, United Kingdom","Santa Clara, United States"],"countries":["GB","US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Chisel","optional":false},{"name":"FIRRTL","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Bluespec","optional":true},{"name":"Confluence","optional":true},{"name":"Git","optional":true},{"name":"GitHub","optional":true},{"name":"Jira","optional":true},{"name":"Scala","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-11-04T00:00:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-06T03:22:43Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nResponsibilities\nArchitect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.\n\nIntegrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.\n\nPerform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.\n\nWork with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.\n\nCollaborate with the performance modeling team for performance exploration and optimization to meet performance goals.\n\nMicroarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.\n\nRequirements\nBS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.\n\n3+ years of design experience.\n\nAcademic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.\n\nProficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.\n\nStrong software engineering skills/background, including:\nObject-oriented, aspect-oriented, and particularly functional programming\n\nTemplated metaprogramming, in any language\n\nCompiler infrastructures, particularly for domain-specific languages\n\nData modeling, particularly intermediate representations for optimizing or transforming compiler passes\n\nTest-driven development, particularly ability to write adaptive unit tests\n\nAttention to detail and a focus on high-quality design.\n\nAbility to work well with others and share the belief that engineering is teamwork.\n\nNice-to-haves\nExperience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.\n\nKnowledge of RISC-V architecture.\n\nExpertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.\n\nKnowledge of verification principles, testbenches, UVM, and coverage.\n\nExperience with Git/Github, Jira, Confluence.\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nUnited KingdomAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. 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