{"id":196283,"url":"https://alion.io/job/sifive-sr-staff-engineer-design-verification","title":"Sr. Staff Engineer - Design Verification","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":72,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":34000,"max_usd":70000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Formal Verification","optional":false},{"name":"Machine Learning","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-02T00:00:00Z","employer_posted_date":"2026-09-02","last_verified_at":"2026-10-20T17:03:36Z","board_verified":true,"closed_at":null,"days_open":49,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":49},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nSummary\nAs a Senior Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex SoC / IP blocks, driving quality from architecture through tape-out. You will define methodology, lead test plan creation, guide junior engineers, and be a key technical partner to architecture, design, and validation teams.\nKey Responsibilities\nVerification Ownership\nOwn verification for one or more complex subsystems (CPU/LSU/cache/interconnect/IP blocks).\n\nDefine verification strategy, methodology, and test plans from spec/architecture documents.\n\nEnsure coverage closure (functional, code, assertion, and scenario coverage) to sign-off criteria.\n\nTestbench Architecture & Implementation\nArchitect and implement constrained-random, coverage-driven testbenches (System Verilog/UVM or equivalent).\n\nDevelop reusable verification components: agents, monitors, scoreboards, checkers, and VIP integrations.\n\nDrive block-level and subsystem-level test environments, including stimulus generation and self-checking.\n\nFormal & Assertion-based Verification\nSpecify and implement assertion sets (SVA or similar) for critical micro-architectural properties.\n\nApply formal verification on key blocks (protocols, arbiter, FIFOs, control logic) to complement simulation.\n\nDebug & Quality\nLead bring-up and debug of complex failures (functional, performance, corner-case, and silicon escapes).\n\nWork closely with RTL designers to root-cause bugs and propose fixes or micro-architectural clarifications.\n\nDefine and track verification metrics; report status, risks, and mitigation plans.\n\nMethodology & Infrastructure\nDefine and evolve DV methodology (UVM usage, regression strategy, coverage methodology, reuse across projects).\n\nCollaborate with CAD/infra teams to improve regressions, farm utilization, CI pipelines, and debug flows.\n\nIntroduce and evaluate new tools/flows (formal, lint, CDC, low-power, emulation/FPGA prototyping).\n\nTechnical Leadership & Mentoring\nProvide technical leadership to DV teams across projects; act as a subject-matter expert for key IP/flows.\n\nMentor junior and mid-level DV engineers in testbench design, debugging, methodology, and best practices.\n\nReview and sign off on test plans, environments, and coverage for other team members.\n\nCross-functional Collaboration\nPartner with architects and RTL designers to refine micro-architecture for verifiability and testability.\n\nCoordinate with software, validation, and post-silicon teams to ensure end-to-end coverage of use-cases.\n\nParticipate in spec reviews, micro-architecture reviews, and tape-out sign-off reviews.\n\nRequired Qualifications\nEducation / Experience\nBS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.\n\nTypically 10+ years of experience in ASIC/SoC/IP design verification, with demonstrated senior/staff-level impact.\n\nTechnical Skills\nStrong expertise in SystemVerilog and UVM (or comparable class-based verification methodologies).\n\nProven experience verifying complex CPU/SoC/IP blocks (e.g., cache/memory subsystem, interconnect, accelerators, IO).\n\nSolid understanding of digital design concepts: pipelines, coherency, memory hierarchy, clocking, resets, CDC.\n\nHands-on experience with:\nFunctional and code coverage, coverage-driven verification.\n\nAssertion-based verification (SVA).\n\nDebug tools (e.g., Verdi, DVE, SimVision) and waveform-based debug.\n\nExperience with industry-standard simulators (VCS, Xcelium, Questa, etc.) and regression infrastructure.\n\nDomain Knowledge\nGood understanding of one or more: CPU microarchitecture (e.g. RISC-V/ARM/x86), cache coherence, memory protocols, on-chip interconnects, or high-speed interfaces.\n\nFamiliarity with standard on-chip/off-chip protocols (e.g. AXI, TileLink).\n\nSoft Skills\nStrong analytical and problem-solving skills; able to drive issues from ambiguity to closure.\n\nExcellent written and verbal communication; comfortable presenting technical topics and status to broader teams.\n\nDemonstrated ability to lead technically across functions and to mentor other engineers.\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. 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