{"id":3528912,"url":"https://alion.io/job/sifive-staff-cpu-design-verification-engineer","title":"Staff CPU Design Verification Engineer","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":76,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":33000,"max_usd":70000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-30T15:19:56Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-10-31T09:13:42Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nSummary\nAs a Staff Hardware Engineer in Design Verification of CPU, you will own verification strategy and execution for complex out-of-order (OOO) processor and cache/memory subsystems. You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape-out.\nKey Responsibilities\nVerification Ownership\nOwn verification of OOO core subsystems, e.g.:\nFront-end: fetch, branch prediction, instruction decode, rename.\n\nBack-end: scheduler/issue queues, execution units, bypass networks.\n\nRetirement & recovery: ROB, commit, exceptions, interrupts, mispredict recovery.\n\nGood knowledge on execution pipelines and multiple execution pipeline scenarios.\n\nMemory subsystem: LSU, TLBs, MMU, L1/L2 caches, coherence, fences, atomics.\n\nDefine verification strategy and test plans from ISA + micro-architecture specs, with emphasis on:\nSpeculative execution, forwarding, hazards, and replay mechanisms.\n\nMemory consistency model (e.g. RVWMO, TSO) and ordering rules.\n\nCoherence/consistency interactions across multi-core systems.\n\nDrive coverage closure (functional, code, assertion, and scenario coverage) to sign-off criteria.\n\nTestbench Architecture & Implementation\nArchitect constrained-random, coverage-driven UVM testbenches for:\nOOO core pipeline (including scoreboards and scoreboard-driven checking).\n\nCache/memory hierarchy, TLB/IOMMU, and coherence protocols.\n\nDevelop reusable verification components: generators for OOO stress (back-to-back branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers.\n\nModel reference behavior (ISA / memory model) for end-to-end checking of:\nInstruction retirement,\n\nRegister and memory architectural state,\n\nFence and atomic semantics.\n\nFormal & Assertion-based Verification\nWrite and maintain assertions for key OOO properties, e.g.:\nNo deadlock or livelock in issue/ROB/LSU.\n\nCorrect flush/replay on branch mispredict, exception, and interrupt.\n\nLoad-store ordering and data-bypass correctness.\n\nApply formal verification to targeted units (e.g. ROB, scoreboard, arbiters, FIFOs, coherence controllers, TLB state machines).\n\nDebug & Quality\nLead debug of complex OOO bugs:\nSubtle ordering violations, rare hazards, corner-case speculation issues.\n\nCoherence races, TLB edge cases, and PMP/privilege interactions.\n\nWork closely with RTL, micro-architecture, and performance teams to root-cause issues and refine designs.\n\nMethodology, Infrastructure, and Leadership\nEvolve DV methodology to efficiently cover OOO behavior:\nScenario libraries for stress (long dependency chains, mixed privilege, multi-thread/multi-core).\n\nMemory model and coherence checkers integrated into the environment.\n\nMentor junior DV engineers on OOO CPU verification, debug strategies, and best practices.\n\nCollaborate cross-functionally with architecture, design, SW, and post-silicon teams to ensure end-to-end coverage of CPU use-cases and customer workloads.\n\nRequired Qualifications:\nEducation / Experience\nBS/MS/PhD in EE/CE/CS or related field.\n\nTypically 8+ years in ASIC/SoC/IP design verification, with significant experience on out-of-order CPU or advanced core projects.\n\nTechnical Skills\nStrong expertise in System Verilog and UVM.\n\nDirect verification experience with OOO CPU micro-architecture, including several of:\nInstruction fetch, decode, rename, and register mapping.\n\nIssue queue / scheduler, physical register files, bypass networks.\n\nReorder buffer, exception/interrupt handling, flush/replay.\n\nLoad-store unit, store buffer, speculative loads/stores, LR/SC and atomics.\n\nTLBs, MMU, page table walkers, and protection (e.g. PMP, virtual memory).\n\nSolid understanding of:\nMemory consistency models (e.g. RVWMO, TSO) and how they map onto hardware.\n\nCoherence protocols and cache hierarchy (L1/L2+, inclusive/exclusive, write-back).\n\nHands-on experience with:\nCoverage-driven verification and coverage closure.\n\nAssertion-based verification (SVA).\n\nDebug tools and large-scale regression environments.\n\nPreferred / Nice-to-Have:\nExperience verifying multi-core OOO systems and inter-core coherence.\n\nExperience with formal verification of OOO structures (e.g. scoreboard, ROB, load-store queues).\n\nExposure to RISC-V or ARM ISA and privilege specs, including virtualization and security extensions.\n\nExperience with performance verification or micro-architectural modeling (to cross-check pipeline behavior).\n\nProven track record of technical leadership on complex CPU or SoC projects (tape-outs, methodology ownership, cross-team initiatives).\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. 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