{"id":922253,"url":"https://alion.io/job/sifive-staff-design-verification-engineer-coherent-interconnect-chi","title":"Staff Design Verification Engineer – Coherent Interconnect (CHI)","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":20,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":93,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Boston, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":188000,"max_usd":347000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":563},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-13T00:00:00Z","employer_posted_date":"2026-09-13","last_verified_at":"2026-11-02T12:37:11Z","board_verified":true,"closed_at":null,"days_open":50,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":50},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nThe Role\nSiFive is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem with a strong focus on CHI-based architecture and protocol behavior.\nIn this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, snoop and home-node interactions, credit- and flow-control behavior, and subsystem integration across multiple interface boundaries. This is a horizontal role with broad impact across the coherent interconnect space, requiring strong technical judgment, deep debug ability, and the ability to influence verification strategy beyond an individually assigned block.\nThis is a Staff Engineer individual-contributor role. We are looking for someone who can define verification strategy, identify architectural and verification gaps early, solve difficult protocol and integration problems, and raise the overall quality bar for the broader interconnect verification effort.\nResponsibilities\nDrive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and ordering\nDevelop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, backpressure, flow control, and error handling\nVerify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation paths\nDefine high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactions\nPartner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff\nAnalyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test content\nImprove methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effort\nContribute to review quality across specifications, verification plans, coverage closure, and debug strategy\nMentor other engineers through technical leadership, design reviews, and verification best practices\nMinimum Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field\n7+ years of experience in ASIC or SoC design verification\nStrong hands-on experience with SystemVerilog-based verification\nStrong understanding of cache-coherent systems, memory subsystems, and on-chip interconnects\nDirect experience verifying coherent protocols, with strong preference for CHI\nStrong understanding of protocol behavior including ordering, snooping, flow control, buffering, arbitration, and error handling\nExperience building reusable checkers, scoreboards, assertions, coverage models, and debug infrastructure\nStrong debugging skills and ability to root-cause issues across specification, RTL, and verification environment layers\nAbility to work effectively across architecture, design, and verification teams in a fast-moving environment\nPreferred Qualifications\nExperience with ARM CHI or similar high-performance coherent interconnect protocols\nExperience verifying large subsystem integration involving coherent caches, bridges, or protocol-conversion paths\nExperience with memory consistency, cache coherency, and weak-ordering verification challenges\nExperience with formal verification, performance-oriented verification, or emulation-assisted debug\nFamiliarity with Python or other scripting languages used for DV infrastructure and automation\nExperience mentoring engineers and driving team-wide improvements in verification quality\nWhat Success Looks Like\nVerification plans are complete, concrete, and aligned to the real architectural and protocol risks\nCritical CHI and coherent-interconnect bugs are found early, reproduced efficiently, and closed with durable fixes\nCoverage and test quality improve meaningfully under your ownership\nThe coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions\nDesign and architecture teams rely on you as a strong technical partner for difficult protocol, coherency, and integration problems\nYou will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.\nBS/MS Degree in EE, CE or CS\n5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification\nDeep understand of computer architecture is desired\nExperienced developer using Object Oriented Programing principles\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.","description_format":"text","description_chars":7415,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Equity","Retirement plans"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-15T02:02:32Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6","filings_12m":6,"filings_prev_12m":10,"green_card_filings_12m":0,"median_offered_wage_usd":162500,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":3}],"liveness":{"score":81,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":0.9,"age_days":50,"expected_fill_days":93,"reasons":["conf:9","velocity","win:mid","comp:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":null,"html_url":"https://alion.io/job/sifive-staff-design-verification-engineer-coherent-interconnect-chi","json_url":"https://alion.io/job/sifive-staff-design-verification-engineer-coherent-interconnect-chi.json","meta":{"generated_at":"2026-11-02T16:14:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22664,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-03T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58802},"rest":"https://alion.io/mcp/rest/get_company?id=58802"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsifive-staff-design-verification-engineer-coherent-interconnect-chi"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsifive-staff-design-verification-engineer-coherent-interconnect-chi"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsifive-staff-design-verification-engineer-coherent-interconnect-chi"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sifive-staff-design-verification-engineer-coherent-interconnect-chi\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsifive-staff-design-verification-engineer-coherent-interconnect-chi"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":922253}},{"tool":"search_jobs","arguments":{"company":"sifive.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":922253},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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