{"id":922252,"url":"https://alion.io/job/sifive-staff-design-verification-engineer-cpu-core-verification-vector","title":"Staff Design Verification Engineer – CPU Core Verification (Vector)","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":20,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":93,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":179000,"max_usd":330000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":563},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-09-13T00:00:00Z","employer_posted_date":"2026-09-13","last_verified_at":"2026-11-03T08:15:04Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nAbout the Role\nSiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with meaningful scope in RISC-V Vector Extension (RVV) and vector microarchitecture verification.\nThis is a Staff individual-contributor role within the CPU Design Verification organization, focused on high-performance out-of-order CPU core development.\nThe role spans key core areas such as Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and Vector Unit / vector microarchitectural interactions, and is aimed at an engineer who can independently own complex verification problems, define verification strategy early, identify microarchitectural risk, and raise verification quality across the broader CPU DV effort.\nYou will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, difficult corner cases are verified thoroughly, and signoff quality is achieved with strong technical judgment and scalable methodology.\nResponsibilities\nOwn verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level verification through core-level integration and signoff.\n\nDrive verification strategy, test planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural interactions.\n\nDefine effective verification approaches for challenging behaviors such as branch prediction, instruction fetch, issue and dispatch behavior, pipeline interactions, hazard handling, load/store ordering, memory consistency, exception and recovery behavior, hardware prefetch correctness, and vector execution correctness.\n\nDrive verification of RVV and vector-unit functionality, including vector arithmetic, vector memory operations, masking behavior, configuration-dependent execution, hazard handling, exception behavior, and scalar-vector interactions.\n\nVerify vector microarchitectural behaviors involving SEW, LMUL, VL, VSTART, masking, vector register-file behavior, vector memory sequencing, and interaction with scalar pipeline and cache / memory hierarchy behavior.\n\nDevelop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.\n\nPartner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness.\n\nDrive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.\n\nContribute reusable methodology, automation, and infrastructure that improve productivity and verification quality across future CPU core programs.\n\nMentor other engineers through technical reviews, debugging guidance, and stronger verification practices.\n\nMinimum Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n7+ years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role.\n\nStrong hands-on experience with SystemVerilog-based verification and modern verification methodologies.\n\nDirect experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.\n\nExperience in one or more CPU core areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, Hardware Prefetch, or Vector Unit verification.\n\nStrong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.\n\nStrong debugging skills and the ability to translate architectural intent into effective verification strategy and execution.\n\nFamiliarity with Python, C/C++, or similar scripting/programming languages used for DV infrastructure and automation.\n\nPreferred Qualifications\nDirect experience with high-performance out-of-order CPU core verification.\n\nDirect experience with RISC-V Vector Extension (RVV), SIMD, or vector-processor verification.\n\nExperience verifying vector behaviors such as vector arithmetic, masking, reductions, permutations, vector-scalar operations, and vector load/store functionality.\n\nExperience verifying vector memory behavior, including alignment, page-boundary conditions, exception handling, hazard detection, cache/memory interactions, and coherency-sensitive scenarios.\n\nExperience working with vector configuration and execution modes such as SEW, LMUL, VL, VSTART, and related legality / corner-case behavior.\n\nExperience verifying complex CPU microarchitectural behaviors involving concurrency, replay, flush, redirects, dependency handling, or weak memory ordering.\n\nExperience developing high-value assertions, checkers, and scoreboards for control-heavy or ordering-sensitive CPU behavior.\n\nExperience using formal verification, emulation, or acceleration for high-risk or hard-to-observe verification problems.\n\nExperience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.\n\nExperience influencing verification methodology beyond immediate ownership scope through reusable infrastructure, automation, or technical leadership.\n\nYou will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.\nBS/MS Degree in EE, CE or CS\n5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification\nDeep understand of computer architecture is desired\nExperienced developer using Object Oriented Programing principles\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.","description_format":"text","description_chars":8468,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Equity","Retirement plans"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-15T02:02:32Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6","filings_12m":6,"filings_prev_12m":10,"green_card_filings_12m":0,"median_offered_wage_usd":162500,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":3}],"liveness":{"score":81,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":0.9,"age_days":51,"expected_fill_days":93,"reasons":["conf:7","velocity","win:mid","comp:brand"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/sifive-staff-design-verification-engineer-cpu-core-verification-vector","json_url":"https://alion.io/job/sifive-staff-design-verification-engineer-cpu-core-verification-vector.json","meta":{"generated_at":"2026-11-03T11:31:58Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15724,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58802},"rest":"https://alion.io/mcp/rest/get_company?id=58802"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsifive-staff-design-verification-engineer-cpu-core-verification-vector"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsifive-staff-design-verification-engineer-cpu-core-verification-vector"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsifive-staff-design-verification-engineer-cpu-core-verification-vector"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sifive-staff-design-verification-engineer-cpu-core-verification-vector\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsifive-staff-design-verification-engineer-cpu-core-verification-vector"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":922252}},{"tool":"search_jobs","arguments":{"company":"sifive.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":922252},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}