{"id":196274,"url":"https://alion.io/job/sifive-staff-design-verification","title":"Staff Design Verification","company":{"id":58802,"name":"SiFive","domain":"sifive.com","url":"https://alion.io/company/sifive","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":72,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":34000,"max_usd":70000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Machine Learning","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-03T12:33:30Z","employer_posted_date":"2026-09-03","last_verified_at":"2026-10-23T08:35:26Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"About SiFive\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.\nAre you ready?\nTo learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.\nJob Description:\nRole Summary\nWe are looking for a Staff Design Verification Engineer to lead the verification of complex out-of-order (OOO) CPU cores and memory subsystems. In this role you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign-off, and act as a technical leader and mentor within the DV team.\nKey Responsibilities\nTechnical Ownership\nOwn DV for major OOO core subsystems such as:\nFront-end: fetch, branch prediction, instruction decode.\n\nRename / register mapping and dependency tracking.\n\nIssue queues / schedulers, execution units, bypass networks.\n\nReorder buffer (ROB), retirement, exceptions, interrupts, and pipeline flush/replay.\n\nLoad-store unit (LSU), store buffer, atomics/LR-SC, fences, speculative loads/stores.\n\nL1 caches, TLBs, MMU interfaces, and coherence/protocol interfaces.\n\nTranslate ISA + micro-architecture specifications into detailed verification plans and test strategies.\n\nTestbench & Methodology Leadership\nArchitect and implement SystemVerilog/UVM testbenches for OOO cores and subsystems:\nReusable UVM environments, agents, monitors, scoreboards, reference models.\n\nConstrained-random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).\n\nDefine and evolve DV methodology for OOO verification:\nScenario libraries for speculation, memory ordering, and multi-core interactions.\n\nReuse patterns across IPs and projects; contribute to common DV infrastructure.\n\nCoverage, Assertions, and Sign-off\nDefine coverage models and sign-off criteria:\nFunctional, code, assertion, and scenario coverage for OOO execution and memory model compliance.\n\nDevelop and maintain assertion sets (SVA) for key OOO properties, such as:\nNo deadlock/livelock in ROB / scheduler / LSQ.\n\nCorrect branch mispredict, exception, and interrupt recovery.\n\nCorrect load-store ordering, forwarding, and replay behavior.\n\nDrive coverage closure and sign-off for owned blocks; review and sign off plans/coverage for peer areas when needed.\n\nDebug & Cross-Functional Collaboration\nLead debug of complex failures:\nSubtle OOO bugs (hazards, wrong-path effects, starvation, corner replay conditions).\n\nMemory ordering and coherence violations across cores and caches.\n\nTLB/MMU and privilege/protection corner cases.\n\nWork closely with:\nMicro-architecture and RTL teams to refine designs for correctness and verifiability.\n\nPerformance/modeling teams to align micro-arch behavior with models and performance targets.\n\nPost-silicon teams to reproduce and root-cause silicon issues in pre-silicon DV.\n\nMentoring & Influence\nMentor junior and mid-level DV engineers in:\nOOO micro-architecture concepts and debug.\n\nTestbench design, stimulus generation, coverage, and methodology.\n\nProvide technical leadership across projects:\nLead DV design and reviews, contribute to architecture/micro-architecture reviews from a verification perspective.\n\nChampion best practices in DV and help set technical direction for core verification.\n\nRequired Qualifications\nEducation: BS/MS/PhD in EE, CE, CS, or related field.\n\nExperience:\nTypically 8+ years of hands-on ASIC/SoC/IP design verification experience.\n\nSignificant experience verifying out-of-order or superscalar CPU cores or similarly complex execution pipelines.\n\nTechnical Skills:\nStrong proficiency in SystemVerilog and UVM (or equivalent class-based methodology).\n\nDeep understanding of CPU micro-architecture, including several of:\nFront-end (fetch, branch prediction, decode).\n\nRename, physical register files, dependency tracking.\n\nSchedulers/issue queues, execution units, bypassing.\n\nROB, commit logic, exception/interrupt/flush paths.\n\nLSU, store buffer, speculative loads/stores, atomics and fences.\n\nL1 caches, TLBs, MMU, and coherence interfaces.\n\nSolid experience with:\nConstrained-random, coverage-driven verification.\n\nWriting and debugging SVA assertions.\n\nMajor simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).\n\nSoft Skills:\nStrong problem-solving and debug skills for complex concurrency/ordering issues.\n\nProven ability to drive technical topics across teams and to completion.\n\nClear communication, both written and verbal; able to present designs, plans, and status to technical and non-technical stakeholders.\n\n Additional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.","description_format":"text","description_chars":6201,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-03T12:33:30Z"}],"visa":[],"liveness":{"score":64,"band":"ok","label":"Likely open","p_open":1,"p_active":0.858,"p_room":0.75,"age_days":50,"expected_fill_days":72,"reasons":["conf:21","velocity","win:late","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/sifive-staff-design-verification","json_url":"https://alion.io/job/sifive-staff-design-verification.json","meta":{"generated_at":"2026-10-25T03:49:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4960,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58802},"rest":"https://alion.io/mcp/rest/get_company?id=58802"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsifive-staff-design-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsifive-staff-design-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsifive-staff-design-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sifive-staff-design-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsifive-staff-design-verification"}]}