{"id":2503731,"url":"https://alion.io/job/signoffsemiconductors-design-engineer-ii-memory-layout","title":"Design Engineer II – Memory Layout","company":{"id":3847785,"name":"Signoffsemiconductors","domain":"signoffsemiconductors.com","url":"https://alion.io/company/signoffsemiconductors","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":14500,"max_usd":35000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":12},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys Custom Compiler","optional":false}],"status":"live","first_seen_at":"2026-10-14T07:00:16Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-15T06:15:27Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"We are seeking a highly motivated Memory Layout Engineer with strong expertise in custom layout development for advanced memory compilers. The ideal candidate will have hands-on experience in SRAM/MRAM layout design, physical verification, and close collaboration with circuit design teams to deliver high-quality layouts for advanced technology nodes.Key\nResponsibilities Design and develop custom layouts for memory macros, including SRAM, MRAM, and other embedded memory architectures. Create and optimize hierarchical layouts for memory sub-blocks such as row decoders, write drivers, sense amplifiers, assist circuits, and memory control logic. Collaborate closely with circuit designers to ensure layout implementation meets performance, area, power, reliability, and manufacturability requirements. Perform and resolve physical verification checks including DRC, LVS, ERC, and reliability-related violations. Analyze and mitigate layout-dependent effects, parasitics, and other second-order effects impacting circuit performance. Drive layout quality, productivity improvements, and best practices across memory design projects. Support project execution across distributed teams and customer engagements. Required Skills & Experience Strong understanding of VLSI fundamentals, including CMOS devices, IC fabrication processes, FinFET technology, and RC network concepts. Hands-on experience in custom memory layout development for SRAM, MRAM, or similar memory architectures. Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, Calibre, ICV, or equivalent. Good understanding of layout optimization techniques involving speed, area, power, parasitics, matching, electromigration, and reliability considerations. Experience working closely with design teams to achieve design specifications and signoff requirements. Strong debugging, problem-solving, and analytical skills. Excellent verbal and written communication skills.\nPreferred\nQualifications Experience with advanced process technologies and high-density memory designs. Ability to independently drive complex layout tasks from concept to tape-out. Experience mentoring junior engineers and leading small technical teams. Strong documentation, presentation, and stakeholder management skills.\nRequirements\nEducation BE/B.Tech in ECE/EEE or M.Tech VLSI Experience 3 - 5 Years Work Environment Flexibility to work from client locations and Offshore Development Centers (ODC) as required. Comfortable working with global cross-functional teams across multiple time zones. Self-driven professional capable of taking ownership and delivering results in a fast-paced environment.\nBenefits As per SignOff Policy","description_format":"text","description_chars":2715,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power Semiconductors","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-14T07:00:16Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":30,"reasons":["conf:3","win:early"],"computed_at":"2026-10-15T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/signoffsemiconductors-design-engineer-ii-memory-layout","json_url":"https://alion.io/job/signoffsemiconductors-design-engineer-ii-memory-layout.json","meta":{"generated_at":"2026-10-15T08:57:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13595,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3847785},"rest":"https://alion.io/mcp/rest/get_company?id=3847785"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsignoffsemiconductors-design-engineer-ii-memory-layout"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsignoffsemiconductors-design-engineer-ii-memory-layout"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsignoffsemiconductors-design-engineer-ii-memory-layout"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/signoffsemiconductors-design-engineer-ii-memory-layout\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsignoffsemiconductors-design-engineer-ii-memory-layout"}]}