{"id":2503733,"url":"https://alion.io/job/signoffsemiconductors-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":3847785,"name":"Signoffsemiconductors","domain":"signoffsemiconductors.com","url":"https://alion.io/company/signoffsemiconductors","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":48000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C++","optional":true},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-08-27T00:00:00Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-10-22T03:46:46Z","board_verified":true,"closed_at":null,"days_open":56,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":56},"description":"Signoff Semiconductors is seeking an experienced ASIC Verification Lead to lead ASIC/SoC/IP verification projects for global semiconductor customers. The role requires strong expertise in functional verification, UVM/SystemVerilog, technical leadership, project execution, and customer engagement.Key\nResponsibilities End-to-end ASIC/SoC/IP verification activities. Define verification plans, methodologies, and sign-off criteria. Develop and review UVM/SystemVerilog-based verification environments. Drive verification execution, debugging, regression, and coverage closure. Collaborate with customers, design teams, and stakeholders to ensure successful project delivery. Ensure quality execution and delivery within project timelines.\nRequirements Required Skills 4-7 years of ASIC/SoC/IP Functional Verification experience. Strong hands-on expertise in SystemVerilog and UVM. Experience developing testbenches, sequences, scoreboards, monitors, drivers, and coverage models. Good understanding of constrained-random and coverage-driven verification methodologies. Experience with simulation, debugging, regression, coverage analysis, verification planning, and sign-off. Strong knowledge of RTL design and digital design concepts. Experience with one or more protocols: AMBA AXI/AHB/APB PCIe Ethernet USB DDR Preferred Skills Python, Perl, or C/C++ scripting. Exposure to Formal Verification, Emulation, FPGA Prototyping, or Post-Silicon Validation. Experience working with global customers and distributed teams.\nEducation B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related field. About Signoff Semiconductors Signoff Semiconductors provides end-to-end VLSI engineering services across ASIC Design, Physical Design, Design Verification, DFT, Analog/Mixed-Signal, FPGA, and Embedded domains. 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