{"id":2204657,"url":"https://alion.io/job/silicon-labs-chip-lead","title":"Chip Lead","company":{"id":44123,"name":"Silicon Labs","domain":"silabs.com","url":"https://alion.io/company/silabs","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":14,"ghost_share":0,"stale_share":0.929,"repost_share":0,"time_to_fill_p50_days":40,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":160650,"max":298350,"currency":"USD","period":"year","gross":null,"usd_annual":298350},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-09T22:45:47Z","employer_posted_date":"2026-10-09","last_verified_at":"2026-10-12T18:56:30Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more atwww.silabs.com.\nChip Lead\nThe Role\nThe Chip Lead provides technical leadership for the architecture, design, integration, and execution of complex wireless System-on-Chip (SoC) products, from initial product definition through silicon bring-up and production.\nThis role requires deep technical expertise in SoC architecture, microarchitecture, and design, including processor subsystems, memory architectures, interconnects, clock and reset architectures, low-power design, digital and mixed-signal IP, and wireless connectivity. The Chip Lead is responsible for translating product requirements into a cohesive SoC architecture, driving key technical decisions and design tradeoffs, and ensuring that the chip meets its functional, performance, power, area, and cost objectives.\nThe Chip Lead works hands-on with engineering teams to drive subsystem design, IP integration, verification, physical implementation, and design closure. The role requires the ability to identify and resolve complex technical issues, challenge design assumptions, evaluate architectural alternatives, and make informed engineering decisions across multiple disciplines.\nAs the overall technical owner of the chip, the Chip Lead coordinates engineering execution across global design teams, establishes technical milestones, manages design dependencies and risks, and drives the SoC through tapeout, silicon bring-up, and production readiness.\nResponsibilities\nLead the technical development and execution of complex wireless SoCs from product definition through design, silicon validation, and production. \nDefinition and Planning \nWork closely with product marketing, systems engineering, and SoC architects to review product requirements and contribute to the definition of the SoC. \nServe as a key stakeholder in SoC architecture development, providing input on architectural decisions, design tradeoffs, technical feasibility, implementation complexity, and IP reuse. \nIdentify technical risks, integration challenges, and cross-functional dependencies early in the development cycle. \nDevelop the chip design execution plan, including technical milestones, design dependencies, and engineering resource requirements. \nProvide technical design collateral and engineering assessments to support product approval gates. \nProject Execution \nProvide hands-on technical leadership throughout SoC design, integration, verification, and physical implementation. \nWork closely with functional and subsystem leads to drive design execution, resolve technical issues, and ensure successful integration of all SoC components. \nReview technical solutions, identify architectural and implementation issues, and collaborate with SoC architects and functional leads to resolve them. \nWork with verification teams to ensure comprehensive SoC verification, including system-level functionality, interfaces, power modes, and critical use cases. \nDrive technical readiness for tapeout, ensuring design completeness, verification closure, and resolution of critical design issues. \nRepresent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure. \nValidation to Production \nProvide technical leadership during silicon bring-up, validation, characterization, and qualification. \nWork closely with validation, software, RF, analog, and product engineering teams to debug complex silicon issues and determine root causes. \nCorrelate silicon behavior with design expectations, simulation results, and architectural specifications. \nDrive resolution of silicon issues through design changes, firmware workarounds, or silicon revisions as appropriate. \nLead technical execution of silicon revisions, including metal-only and full-layer respins when necessary. \nEnsure the SoC meets its functional, performance, power, and quality requirements before production release. \nSkills you will need:\nCapable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus. \nTop-down planning and execution of SOC projects. \nExperience in full-chip development cycle \nAble to build strong technical team. \nHands-on experience in architecture, micro-architecture, digital design processes \nKnowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI \nKnowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc. \nKnowledge of processors like RISC-V and ARM processors \nKnowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure \nKnowledge of DFT including Scan, ATPG, MBIST \nKnowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) \nKnowledge of hardware accelerators \nKnowledge of Verilog and System Verilog \nKnowledge of scripting languages like Perl, Python, Tcl, shell \n12+ years of experience with Bachelor or Master’s degree in Electrical or Computer Engineering \nBenefits & Perks\nYou can look forward to the following benefits: \nGreat medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans\nHighly competitive salary\n401k plan with match and Roth plan option\nEquity rewards (RSUs)\nLife/AD&D and disability coverage\nFlexible spending accounts\nAdoption assistance\nBack-Up childcare\nAdditional benefit options (Commuter benefits, Legal benefits, Pet insurance)\nFlexible PTO schedule\n3 paid volunteer days per year\nCharitable contribution match\nTuition reimbursement\nFree downtown parking\nOnsite gym\nMonthly wellness offerings\nFree snacks\nCompany updates with our CEO\nThe annualized base pay range for this role is expected to be between $160,650 - $298,350 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.\nSilicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.","description_format":"text","description_chars":7044,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["401k plan","Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Embedded Software & RTOS","RF & Wireless Hardware","IoT Platforms & Solutions","Smart City"],"lifecycle":[{"event":"open","at":"2026-10-09T22:45:47Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":40,"reasons":["conf:1","stale_co","velocity","win:early"],"computed_at":"2026-10-12T06:55:09Z"},"pay":{"stated_usd_annual":298350,"is_top_pay":true},"html_url":"https://alion.io/job/silicon-labs-chip-lead","json_url":"https://alion.io/job/silicon-labs-chip-lead.json","meta":{"generated_at":"2026-10-13T01:02:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1539,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":44123},"rest":"https://alion.io/mcp/rest/get_company?id=44123"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsilicon-labs-chip-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsilicon-labs-chip-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsilicon-labs-chip-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/silicon-labs-chip-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsilicon-labs-chip-lead"}]}