{"id":1400749,"url":"https://alion.io/job/silicon-labs-senior-engineer-ic-design-rtl-ams","title":"Senior Engineer - IC Design (RTL AMS)","company":{"id":44123,"name":"Silicon Labs","domain":"silabs.com","url":"https://alion.io/company/silabs","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":15,"ghost_share":0,"stale_share":0.933,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":48000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence AMS Designer","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-28T15:25:24Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-30T13:52:43Z","board_verified":true,"closed_at":null,"days_open":32,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":32},"description":"Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more atwww.silabs.com.\nRole Overview\nThe RTL Design Engineer for Mixed-Signal IPs is responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems that combine analog and digital functionalities. This role requires a deep understanding of digital design principles, interface with analog/mixed-signal teams, and strong verification and integration skills to ensure high-quality, low-power, and functionally robust IP delivery. The engineer will work closely with system architects, analog designers, and SoC teams to enable seamless integration of mixed-signal IPs into complex SoCs.\nKey Responsibilities\nDevelop synthesizable, high-quality RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.\nCollaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols.\nEnsure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.\nParticipate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces.\nPerform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.\nCollaborate with verification engineers to define test plans, drive coverage closure, and debug issues across digital and analog boundaries.\nIntegrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing issues during full-chip validation.\nContribute to continuous improvement of design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.\nQualifications\n3+ years of experience in digital RTL design with strong exposure to mixed-signal IP or subsystem development.\nProficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC).\nFamiliarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power management.\nHands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.) is a plus.\nGood understanding of digital communication protocols (SPI, I2C, APB, AXI).\nExposure to scripting (Python, Perl, TCL) for automation and design flow enhancements.\nExperience working in cross-functional environments involving analog, verification, and SoC integration teams.\nEducation\nB.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering.\nKey Competencies\nStrong understanding of digital design and verification fundamentals.\nAbility to work effectively across analog and digital domains in a collaborative environment.x\nExcellent debugging, problem-solving, and analytical skills.\nGood communication and documentation abilities.\nPassion for quality, efficiency, and innovation in mixed-signal IP design.\nSuccess Metrics\nTimely delivery of functionally correct and synthesis-ready RTL for mixed-signal IPs.\nHigh quality and robustness verified through simulation, lint, and CDC sign-off.\nEffective collaboration with analog and SoC teams ensuring smooth IP integration.\nContributions to methodology and flow improvements enhancing team efficiency.\n\" Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making\"\nBenefits & Perks :\nNot only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.\nEquity Rewards (RSUs)\nInsurance plans with Outpatient cover\nNational Pension Scheme (NPS)\nFlexible work policy\nChildcare support\nSilicon Labs is an equal opportunity employer and values the diversity of our employees. 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