{"id":3202571,"url":"https://alion.io/job/silicon-labs-static-timing-analysis-engineer","title":"Static Timing Analysis Engineer","company":{"id":44123,"name":"Silicon Labs","domain":"silabs.com","url":"https://alion.io/company/silabs","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":15,"ghost_share":0,"stale_share":0.933,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":160650,"max":298350,"currency":"USD","period":"year","gross":null,"usd_annual":298350},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-22T00:00:00Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-31T03:25:53Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more atwww.silabs.com.\nStatic Timing Analysis Engineer\nAustin, TX \nThis position involves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML and are specified to exceed best-in-class power targets. These SoCs deploy a complex, deeply gated clock network with many asynchronous clock sources.\nResponsibilities\nDevelop timing constraints at both the IP and SoC level in collaboration with the designers\nImprove or evolve existing static timing analysis flows and methodologies. \nDevelop required timing signoff criteria, such as aging, on chip variation, and signal integrity\nAnalyze timing reports using scripting techniques to develop insights and drive rapid timing closure\nCollaborate with a global design team to resolve complex static timing issues\nCollaborate with a multi-functional team to drive timing closure for mixed-signal IP integration\nSkills You Will Need \nMinimum Qualifications \nBachelor or master’s degree in electrical or computer engineering and 8+ years’ experience\nIn depth knowledge of the timing closure flow and methodology\nExperience in timing constraint development, both functional and test modes (such as scan)\nHands-on experience with static timing tools, such as Tempus or Primetime\nIn depth knowledge of scripting languages like Perl, Python, Tcl, shell\nKnowledge of timing closure modes and corners\nKnowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)\nKnowledge of timing model generation of mixed signal IP\nKnowledge of design flows including Lint, CDC, Synthesis, Logic Equivalence, DFT, Place and Route\nKnowledge of Verilog and System Verilog\nBenefits & Perks\nYou can look forward to the following benefits: \nGreat medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans\nHighly competitive salary\n401k plan with match and Roth plan option\nEquity rewards (RSUs)\nLife/AD&D and disability coverage\nFlexible spending accounts\nAdoption assistance\nBack-Up childcare\nAdditional benefit options (Commuter benefits, Legal benefits, Pet insurance)\nFlexible PTO schedule\n3 paid volunteer days per year\nCharitable contribution match\nTuition reimbursement\nFree downtown parking\nOnsite gym\nMonthly wellness offerings\nFree snacks\nCompany updates with our CEO\nThe annualized base pay range for this role is expected to be between $160,650 - $298,350 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.Silicon Labs is an equal opportunity employer and values the diversity of our employees. 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