{"id":3550313,"url":"https://alion.io/job/sitime-principal-physical-design-engineer","title":"Principal Physical Design Engineer","company":{"id":58930,"name":"SiTime","domain":"sitime.com","url":"https://alion.io/company/sitime","size_band":"1-10","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tempe, United States","Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":107000,"max_usd":216000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1961},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Compiler II","optional":false}],"status":"live","first_seen_at":"2026-10-30T19:38:20Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-11-02T07:20:05Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About SiTime\nSiTime is the Precision Timing company.\nTiming is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.\nOur semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.\nJob Summary\nSiTime is seeking a seasoned Principal Physical Design Engineer to lead the physical implementation and signoff of complex digital blocks and subsystems. The successful candidate will take end-to-end ownership from synthesis and floorplanning through GDSII signoff, driving power, performance, area, reliability, and schedule outcomes.This role serves as a technical leader for physical design, shaping implementation methodology and automation, resolving complex cross-functional challenges, and establishing engineering best practices across multiple programs.\nWe value diverse experiences, perspectives, and career paths, and welcome candidates who are excited to contribute to our mission.\n Responsibilities:\nServe as the technical focal point for physical design, leading implementation and signoff reviews, mentoring engineers, and establishing reusable methodologies across multiple programs.\nLead and execute end-to-end physical design for complex digital blocks and subsystems, from synthesis through GDSII signoff, including floorplanning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal equivalence check, design rule checking (DRC), layout versus schematic (LVS), power, and EMIR.\nDevelop and continuously improve automated, reproducible physical-design and signoff flows to increase productivity, reduce execution risk, and ensure consistent design quality across multiple programs.\nParticipate actively in architecture and design-specification reviews, providing physical-implementation insight early to avoid downstream PPA, signoff, and schedule risks.\nArchitect and apply low-power implementation strategies including clock gating, power gating, power-aware implementation and multi-voltage design to meet product-level power budgets.\nWork closely with the chip-top layout and integration teams to integrate digital blocks into mixed-signal, custom-layout top-level designs, resolving physical, DRC, LVS, power, clock, EMIR, and connectivity issues at block boundaries.\nIt is not necessary to meet all job requirements to be a qualified candidate for the position. \nQualifications & Requirements: \nBS. in Electrical Engineering, Computer Engineering, or a related field with a minimum of 10 years of relevant experience, or a Ph.D. with a minimum of 6 years of relevant experience.\nHands-on ASIC physical design experience, with a clear record of driving designs from concept through successful tape-out on advanced process nodes.\nDeep hands-on experience with industry-standard physical implementation and signoff tools, such as Cadence Innovus or Synopsys IC Compiler II/Fusion Compiler, together with STA, formal, physical-verification, and power-integrity platforms.\nStrong scripting capability in Tcl, Perl, and/or Python, applied to flow automation, constraint generation, and custom reporting.\nStrong understanding of SDC timing constraints and concurrent MMMC optimization throughout the physical design cycle (Placement, CTS, and Routing).\nThorough knowledge of STA concepts, constraints and methodologies.\nHands-on experience setting up and executing functional and timing ECOs through industry-standard ECO flows to signoff.\nStrong analytical and problem-solving instincts, and the ability to communicate complex technical trade-offs clearly to both peers and leadership.\nDrive technical alignment across cross-functional teams by communicating implementation constraints, design trade-offs, and execution risks, and by influencing decisions that impact PPA, signoff, and schedule.\nEnglish proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.\nDesired Characteristics & Attributes:\n12+ years of relevant physical-design experience, including technical leadership across multiple tape-outs.\nPrior experience bringing up Place & Route (PnR) flow from scratch\nProven experience implementing low-power methodologies including clock gating, power gating, and multi-voltage domain design.\nExperience in dynamic and static power analysis, EMIR analysis, and driving corrective actions to meet signoff targets.\nSolid understanding of semiconductor process technology, device physics, and Design for Manufacturability (DFM) principles that affect physical implementation decisions.\nDemonstrated ability to drive multiple chip implementations in parallel while maintaining schedule and signoff quality.\nCompensation: \nAt SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.\nIn addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals-reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.\nBenefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.\nSiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.\nLearn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. \nInnovation on Top - Philosophies of Innovation with Rajesh Vashist\nFabrication Knowledge - An Interview with Rajesh Vashist\n SiTime Corporation - YouTube","description_format":"text","description_chars":6767,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":["401k plan","Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Passive Components & Connectors","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-30T22:21:43Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 19 · green card filings: 3","filings_12m":19,"filings_prev_12m":10,"green_card_filings_12m":3,"median_offered_wage_usd":140455,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":26,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":null,"html_url":"https://alion.io/job/sitime-principal-physical-design-engineer","json_url":"https://alion.io/job/sitime-principal-physical-design-engineer.json","meta":{"generated_at":"2026-11-02T10:15:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14249,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-03T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58930},"rest":"https://alion.io/mcp/rest/get_company?id=58930"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsitime-principal-physical-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsitime-principal-physical-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsitime-principal-physical-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sitime-principal-physical-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsitime-principal-physical-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3550313}},{"tool":"search_jobs","arguments":{"company":"sitime.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3550313},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}