{"id":3481279,"url":"https://alion.io/job/sitime-sr-engineer-layout-design","title":"Sr. Engineer, Layout Design","company":{"id":58930,"name":"SiTime","domain":"sitime.com","url":"https://alion.io/company/sitime","size_band":"1-10","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tokyo, Japan"],"countries":["JP"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Virtuoso","optional":false}],"status":"live","first_seen_at":"2026-10-16T01:21:25Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-10-30T22:21:43Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"About SiTime\nSiTime is the Precision Timing company.\nTiming is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.\nOur semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.\nJob Summary\nThe Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality\nResponsibilities:\nRequires remote interfacing with local and global design and layout teams in multiple design centers across different time zones\nLead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits\nPerform schematic-driven layout and design constraints\nDesign die-area efficient layouts according to circuit designer requirements\nPerform block or top-level layout designs\nPerform floor-planning, power line planning, shielding, and device-matching layout\nVerify layouts. Pass DRC, LVS, and ERC\nContribute to various chip-level routing and layout needs\nPerform chip level integration, verifications, and tape-out\nSupport other projects as needed by management\nTrain junior layout engineers and offshore layout contractors\nContribute to developing common best practices and workflow across all sites \nContribute to build process and procedures to achieve high layout quality\nQualifications & Requirements:\nBA/BS Degree in Layout Design or related field or equivalent experience\n10 years’ experience with layout design for analog and full-custom digital blocks\nExperience TSMC 180nm, 65nm, 22nm process technologies\nProficient in using layout editing tools in the Cadence Virtuoso design environment\nSolid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre\nConceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation\nStrong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints\nExperience in chip-level floor planning and analog block integration\nExperience chip level integration, verifications, and tape-out\nAbility to use productivity-enhancing tools and design scripts to further automate tasks is also desirable\nMust be able to lift, push, and pull up to 5 lbs\nDesired Characteristics & Attributes:\nAttention to detail, organized, accurate and can produce efficient layout techniques\nHas a good track record of on time work delivery\nHas a self-motivated, team player with good communication skills\nAbility to work well with others in a fast-paced collaborative team environment\nCompensation Range: \nAt SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.\nIn addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals-reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.\nSiTime is committed to providing equal employment opportunities to all employees and applicants. Employment decisions are based on qualifications, merit, and business needs. We do not discriminate on the basis of any characteristic protected by applicable law.\nLearn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. \nInnovation on Top - Philosophies of Innovation with Rajesh Vashist\nFabrication Knowledge - An Interview with Rajesh Vashist\n SiTime Corporation - YouTube","description_format":"text","description_chars":4695,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Passive Components & Connectors","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-29T20:14:17Z"}],"visa":[],"liveness":{"score":76,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.839,"p_room":0.9,"age_days":14,"expected_fill_days":27,"reasons":["conf:1","win:mid","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/sitime-sr-engineer-layout-design","json_url":"https://alion.io/job/sitime-sr-engineer-layout-design.json","meta":{"generated_at":"2026-10-31T00:38:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":865,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58930},"rest":"https://alion.io/mcp/rest/get_company?id=58930"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsitime-sr-engineer-layout-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsitime-sr-engineer-layout-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsitime-sr-engineer-layout-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sitime-sr-engineer-layout-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsitime-sr-engineer-layout-design"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3481279}},{"tool":"search_jobs","arguments":{"company":"sitime.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3481279},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}