{"id":1272701,"url":"https://alion.io/job/skywaves-rise-lead-dft-engineer-2","title":"Lead DFT Engineer","company":{"id":3808958,"name":"Skywaves Rise","domain":"skywavesgroup.net","url":"https://alion.io/company/skywaves-rise-2","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19500,"max_usd":49000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys TestMAX","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-09-01T03:53:29Z","employer_posted_date":null,"last_verified_at":"2026-09-01T03:53:29Z","board_verified":false,"closed_at":null,"days_open":66,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":66},"description":"About the Role : \n\nWe are looking for a Lead DFT Engineer to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG, enabling high-quality silicon with optimal test coverage.\n\nWhat You'll Do : \n\n- Define and implement DFT architecture for complex SoCs and IPs.\n\n- Drive Scan Insertion, scan compression, scan stitching, and scan verification.\n\n- Develop and integrate MBIST solutions for embedded memories and memory repair flows.\n\n- Generate and optimize ATPG patterns for stuck-at, transition, and advanced fault models.\n\n- Perform DFT verification, coverage analysis, pattern validation, and debug.\n\n- Collaborate with RTL, Physical Design, STA, and Test Engineering teams to achieve DFT closure.\n\n- Drive DFT sign-off, improve test coverage, and optimize test time and silicon quality.\n\n- Develop automation scripts to improve DFT productivity and flow efficiency.\n\nWhat We're Looking For : \n\n- 10 - 12 years of hands-on experience in Design for Test (DFT).\n\n- Strong expertise in Scan Insertion, scan compression, and scan architecture.\n\n- Deep experience with MBIST implementation, integration, and verification.\n\n- Strong knowledge of ATPG generation, fault simulation, and coverage optimization.\n\n- Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or equivalent.\n\n- Understanding of JTAG/IEEE 1149.1, boundary scan, and IEEE 1500 standards.\n\n- Experience with DFT validation, gate-level simulation, and scan debug.\n\n- Proficiency in TCL, Python, or Perl scripting for flow automation.\n\n- Excellent debugging, analytical, and cross-functional collaboration skills.\nSkills\nDFT, MBIST, SoC, ATPG, RTL, Physical Design, Static Timing Analysis, Synopsys, TCL, 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