{"id":4196615,"url":"https://alion.io/job/smartsoc-solutions-rtl-lec-engineer","title":"RTL LEC Engineer","company":{"id":4540030,"name":"SmartSoC Solutions","domain":"smartsocs.com","url":"https://alion.io/company/smartsoc-solutions","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-12T20:35:00Z","employer_posted_date":null,"last_verified_at":"2026-11-12T20:35:00Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"We are looking for a skilled LEC Engineer with hands-on experience in Logical Equivalence Checking using Cadence Conformal. The candidate will be responsible for setting up LEC flows, performing equivalence checks, debugging mismatches, and ensuring logical consistency between RTL and synthesized netlists.\n\nKey Responsibilities:\nSet up, configure, and execute Logical Equivalence Checking (LEC) flows using Cadence Conformal.\nPerform RTL-to-gate-level and gate-to-gate equivalence checking.\nDebug and resolve equivalence failures, mismatches, and non-equivalent compare points.\nAnalyze RTL, synthesized netlists, and formal verification reports.\nConfigure tool settings, constraints, libraries, and design setup files.\nIdentify and resolve issues related to synthesis transformations, naming mismatches, and design optimizations.\nCollaborate with RTL design, synthesis, and physical design teams to resolve functional equivalence issues.\nAutomate and improve LEC flows using scripting languages such as Tcl, Perl, or Python.\nEnsure successful LEC sign-off for block-level and/or full-chip designs.\n\nRequired Skills:\nHands-on experience with Cadence Conformal for Logical Equivalence Checking.\nStrong experience in LEC flow setup, configuration, execution, and debugging.\nKnowledge of RTL-to-netlist and gate-to-gate equivalence verification.\nUnderstanding of Verilog/SystemVerilog and synthesized netlists.\nFamiliarity with synthesis concepts, including logic optimization, retiming, and design transformations.\nAbility to analyze LEC reports and troubleshoot equivalence failures.\nScripting knowledge in Tcl, Perl, or Python.\n\nPreferred Qualifications:\nExperience with formal verification methodologies and semiconductor ASIC/SoC design flows.\nExposure to synthesis tools and RTL design/debugging.\nUnderstanding of low-power design techniques, scan insertion, and DFT-related transformations.\nExperience in block-level or full-chip LEC sign-off.\n\nEducation:\nBachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.\nSkills\nCadence Conformal, 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