{"id":2765979,"url":"https://alion.io/job/spinncloud-senior-noc-research-engineer-network-on-chip","title":"Senior NoC Research Engineer (Network-on-Chip)","company":{"id":3793739,"name":"SpiNNcloud","domain":"spinncloud.com","url":"https://alion.io/company/company-website-7","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"softgarden","truth_index":null},"role":"AI/ML","role_family":"AI/ML","seniority":"senior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Germany"],"countries":["DE"],"hiring_countries":["DE"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":81000,"max_usd":166000,"period":"year","method":"role_seniority_country_cell","sample_n":18},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"HPC","optional":false},{"name":"InfiniBand","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-13T14:57:15Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-24T15:35:40Z","board_verified":true,"closed_at":null,"days_open":11,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":11},"description":"Senior NoC Research Engineer (Network-on-Chip)About SpiNNcloud\nSpiNNcloud Systems is a pioneering deep-tech company developing brain inspired computing hardware and software based on the SpiNNaker2 technology. Our platform provides remote access to cutting-edge sparse computing resources, enabling breakthroughs in AI, HPC, and energy-efficient computing.\nRole Overview\nWe are seeking a Senior Network-on-Chip (NoC) Research Engineer to shape the on-chip and chip-to-chip interconnect of SpiNNext, our next-generation chip. In systems built from very large numbers of cores, moving data efficiently determines both performance and energy efficiency. You will model, simulate and evaluate interconnect architectures under real ML workloads, and turn your findings into quantitative design decisions. You will report to our CTO and work closely with our chip architecture, hardware and software teams.\nKey Responsibilities\nInterconnect Architecture & Modelling\nExplore and evaluate NoC topologies, router and switch designs, arbitration, flow control, QoS and congestion control\nBuild and maintain architectural models and simulations, using SST, gem5 or custom cycle-level and analytical models\nDevelop traffic generators that reflect real ML workloads: collective communication, tensor parallelism and memory traffic\nPerformance Analysis & Design Trade-offs\nAnalyse power, performance and area (PPA) trade-offs and back recommendations with quantitative evidence\nEnsure deadlock- and livelock-free designs through analysis, formal methods or simulation\nInvestigate adaptive routing strategies and topology options\nProtocols, IP & Scale-out\nTranslate complex protocol and IP specifications (AXI, CHI, APB) into clear design requirements\nEvaluate third-party interconnect IP and support build-versus-buy decisions\nAssess how RDMA concepts and chip-to-chip interfaces shape data movement between accelerators at system scale\nResearch & Collaboration\nPresent findings and recommendations to architecture and leadership teams\nContribute to publications and patents in on-chip networks and data movement for ML\nRequired Qualifications\nEducation & Experience\nPhD, or Master's with equivalent research experience, in Electrical Engineering, Computer Engineering, Computer Science or a related field\nSenior-level track record in NoC or interconnect architecture, in industry or applied research\nTechnical Skills\nStrong background in on-chip interconnect and traffic management: NoC topologies, routers and switches, arbitration, flow control, QoS and congestion control\nGood understanding of ML workloads and accelerator architectures, including how collective communication, tensor parallelism and memory traffic stress the interconnect\nWorking knowledge of on-chip protocols such as AXI, CHI or AHB\nUnderstanding of RDMA concepts and transports (InfiniBand, RoCE), including queue pairs, memory registration and zero-copy transfers\nExperience reasoning about PPA trade-offs with quantitative evidence\nHands-on architectural modelling and simulation (SST, gem5 or own models), with strong Python and C++\nAbility to read complex protocol and IP specifications and turn them into clear design requirements\nExperience with deadlock and livelock avoidance, adaptive routing or topology exploration\nClear written and verbal communication in English, and a proactive, collaborative approach to open-ended problems\nPreferred Qualifications\nExperience with chip-to-chip and die-to-die interfaces such as PCIe, Ethernet or UCIe\nExperience with memory subsystems such as HBM and CXL\nPublications or patents in on-chip networks, interconnect architecture, or data movement for ML or HPC\nFamiliarity with massively parallel architectures\nWhat We Offer\nCompetitive salary based on experience\n30 days annual vacation, up to 2 weeks of work abroad\nWork on cutting-edge sparse computing technology\nHigh-impact role with direct influence on the architecture of SpiNNext\nCollaborative team culture with experienced engineers from academia and industry\nEquity participation in a growing deep-tech company\nHow to Apply\nPlease include:\nCV highlighting relevant interconnect, NoC or architecture research experience\nBrief cover letter describing an interconnect or data-movement problem you analysed and what you recommended\nLinks to publications, patents or public code (optional)\nSalary expectations and earliest start date\nYour current location, and whether you would need visa sponsorship and/or relocation support to work in Germany.\nSpiNNcloud Systems is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We encourage applications from candidates of all backgrounds, regardless of race, gender, age, disability, sexual orientation, or national origin.","description_format":"text","description_chars":4806,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"Upper-Intermediate (B2)","optional":false}]},"benefits":["Equity"],"hiring_locations":[{"name":"Germany","iso":"DE","kind":"country"}],"hiring_excludes":[],"relocation_offered":true,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-17T04:00:50Z"}],"visa":[],"liveness":{"score":74,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.825,"p_room":0.9,"age_days":10,"expected_fill_days":29,"reasons":["conf:3","velocity","win:mid"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/spinncloud-senior-noc-research-engineer-network-on-chip","json_url":"https://alion.io/job/spinncloud-senior-noc-research-engineer-network-on-chip.json","meta":{"generated_at":"2026-10-24T18:47:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27441,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3793739},"rest":"https://alion.io/mcp/rest/get_company?id=3793739"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fspinncloud-senior-noc-research-engineer-network-on-chip"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fspinncloud-senior-noc-research-engineer-network-on-chip"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fspinncloud-senior-noc-research-engineer-network-on-chip"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/spinncloud-senior-noc-research-engineer-network-on-chip\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fspinncloud-senior-noc-research-engineer-network-on-chip"}]}